Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-06-27
2004-04-06
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06717870
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for assessing the quality of a memory unit having a multiplicity of memory cells, in which the memory cells are addressed through word lines running in one direction and bit lines running in another direction and the defective memory cells are detected.
Such methods are generally known and are used for testing the memory units, which are generally memory chips, with regard to their function. In such a case, these methods are employed in various stages of the production process. It is customary, e.g., for the function of the memory units to be tested and, if appropriate repaired while still on a wafer. Afterward, the wafers are usually separated to form individual memory chips and the memory chips are introduced into the housing. In a further method step, the finished memory devices are subjected to a thermal treatment, also referred to as “burn-in”. During this, the memory devices are also exposed to electrical stress and tested in the process. The memory devices are thereupon tested at the specified speed at different temperatures. The memory components are subsequently mounted on circuit boards. This produces memory modules that are tested anew prior to delivery.
One disadvantage of the prior art methods is that the memory unit has to be tested at least three times before delivery. The first time, the memory units are tested on the wafer with regard to their function. The second test is carried out with the finished memory devices, and, finally, the finished memory modules are tested.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for assessing the quality of a memory unit that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that effectively determines the quality of memory units.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for assessing the quality of a memory unit having a multiplicity of memory cells, including the steps of addressing the memory cells through word lines running in one direction and bit lines running in another direction, detecting defective ones of the memory cells, determining a number of word lines and/or bit lines for each word line and/or bit line in which a number of defective memory cells exceeds a limit value, and determining a number of defective memory cells along further ones of the word and/or bit lines running in the same direction for each word and/or bit line in which the number of defective memory cells is at most equal to the limit value.
The number of word lines or bit lines is determined in the case where the number of defective memory cells exceeds a limit value, and that the number of defective memory cells along further lines of the word lines or bit lines that run in the same direction is determined in the case where the number of defective memory cells is at most equal to the limit value.
The method according to the invention makes it possible to assess the quality of a memory unit without having to repair all the memory cells prior to the thermal treatment. The advantage occurs because the method according to the invention excludes the case where an entire control line with the memory cells connected thereto slowly degrades during the thermal treatment. Consequently, only those memory cells along the control lines are assessed that are actually activated in the finished memory component. The degraded control lines need not, however, be used to assess the quality of the memory units because these are deactivated in the finished memory component. It suffices, therefore, to subject the memory units, without a prior test and without prior repairs, to a thermal treatment until the method according to the invention indicates a stable state, in order subsequently to carry out the required repairs.
In accordance with another mode of the invention, the memory unit is exposed to an elevated temperature and repeatedly written to and read from the memory cells while carrying out the addressing, detecting, and determining steps.
In accordance with a further mode of the invention, each of word and/or bit lines are serially checked one after the other and, after each complete check of one of the word and/or bit lines, the number of defective memory cells detected are compared with the limit value, and, where the number of defective memory cells detected exceeds the limit value, a line defect counter is incremented and, where the number of defective memory cells detected does not exceed the limit value, in a summer, the number of defective memory cells detected in the respective line checked is added to the already detected total number of defective memory cells.
In accordance with an added mode of the invention, there is used, for the limit value, a number less than a number of redundant ones of the bit lines.
In accordance with an additional mode of the invention, there is used, for the limit value, a number less than a number of redundant ones of the word lines.
In accordance with yet another mode of the invention, before the temperature is elevated, a functional test is carried out without repairing elements identified as defective.
In accordance with yet a further mode of the invention, after the temperature is elevated, a repair of defective memory cells is carried out by redundant elements.
In accordance with yet an added mode of the invention, after the temperature is elevated, a repair of defective memory cells is carried out using redundant memory cells.
In accordance with a concomitant mode of the invention, after the temperature is elevated, a repair of defective memory cells is carried out using at least one of redundant word lines, redundant bit lines, and redundant memory cells.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for assessing the quality of a memory unit, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from-the following description of specific embodiments when read in connection with the accompanying drawings.
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patent: 6434063 (2002-08-01), Nishio et al.
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Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Phan Trong
Stemer Werner H.
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