Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2003-05-30
2004-11-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C365S063000
Reexamination Certificate
active
06822335
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for arranging power supply lines in a semiconductor device, and more particularly, to a method for arranging a power reinforcing line for uniformly and supplying a stable power supply voltage, a ground voltage, and a boosting voltage to a sense amplifier of a semiconductor device.
2. Description of the Related Art
As semiconductor devices become highly integrated, the design rule and chip sizes are reduced. On the other hand, it becomes necessary to suppress signal delay in RC circuits and supply power with stability. In order to meet these needs, a technology has been developed to increase the width of a metal layer (interconnections) that comprises a power supply line for supplying power to a semiconductor device. In a dynamic random access memory (DRAM) of 64M or more, the metal layer of a double layer excluding word lines and bit lines, has been used as a power supply line by using the metal layer of a double layer as an interconnection. However, for a DRAM of 1 gigabyte, it is difficult to supply stable power to the device by using only the metal layer of a double layer. The problem will be described further with reference to FIG.
1
.
A plurality of DRAM memory cells (not shown) having a matrix arrangement are included in each of the plurality of memory cell array blocks
10
. Sub-word line drivers
18
are arranged adjacent to the memory cell array blocks
10
in the direction to which word lines (not shown) are extended, and sense amplifiers
16
are arranged adjacent to the memory cell array blocks
10
in the direction to which bit lines (not shown) are extended. The sense amplifiers
16
are connected to column decoders
12
arranged parallel to the sense amplifiers
16
, and the sub-word line drivers
18
are connected to row decoders
14
arranged parallel to the sub-word line drivers
18
. A normal word line enabling signal (not shown) output from one of the row decoders
14
is supplied via first interconnections
20
to the sub-word line drivers
18
located along the same rows as the above row decoder
14
. A column selection signal (not shown) output from one of the column decoders
12
is supplied via a first group
22
a
of the second interconnections
22
to the sense amplifiers
16
located along the same columns as the above column decoder
12
. Operating voltages, such as a power supply voltage, a ground voltage, and a boosting voltage, are supplied to the sense amplifiers
16
via a second group
22
b
of the second interconnections
22
.
When a predetermined normal word line enabling signal is selected, a neighboring first interconnection
20
, one of the first interconnections
20
used for transmitting the selected signal is affected by coupling noise or parasitic capacitance. Also, when the selected normal word line enabling signal is transmitted from the closest first sub-word line driver
18
arranged closely to the low decoder
14
to the furthest sub-word line driver
18
from the low decoder
14
, a signal delay inevitably occurs. In order to reduce the signal delay, the width of the first interconnections
20
for transmitting the normal word line enabling signal NWEi is increased. However, this causes an interval between the first interconnections
20
to become narrower and coupling noise or parasitic capacitance to increase.
As a result, a technology for forming second interconnections
22
having a second group
22
b
on the sense amplifiers
16
arranged between the memory cell array blocks
10
has been suggested. However, since a power supply line is formed on the sense amplifiers
16
occupying a narrow region, the power supply line is arranged at narrow intervals. Thus, noise is caused by the power supply line, and it is difficult to obtain a margin in a process of forming contact plug for connecting the power supply line to the sense amplifiers
16
.
Further, since the number of the sense amplifiers
16
is increased by the abovementioned two technologies according to an increase in density, as the power required for operation, such as the power supply voltage is transmitted, the power is consumed. Thus, it is difficult to maintain operating voltages in the sense amplifiers
16
.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first objective of the present invention to provide a method for arranging a power supply line for the purpose of supplying stable power to a sense amplifier in a semiconductor device.
It is a second objective of the present invention to provide a semiconductor device having a power supply line capable of supplying stable power to a sense amplifier.
Accordingly, to achieve the first objective, there is provided a method for arranging a power supply line in a semiconductor device including a plurality of memory cell array blocks. In the method, a plurality of first interconnections that extend in one direction and are spaced apart from one another are arranged on a semiconductor substrate on which the plurality of memory cell array blocks are formed. The plurality of first interconnections have a pitch corresponding to two pairs of word lines arranged on each of the plurality of memory cell array blocks. A first insulating layer is formed on the plurality of first interconnections. A plurality of power reinforcing lines that extend in one direction and are spaced apart from one another on the plurality of first interconnections are arranged on the first insulating layer. A second insulating layer is formed on the plurality of power reinforcing lines. A plurality of second interconnections that intersect the plurality of first interconnections and the plurality of power reinforcing lines are arranged on the second insulating layer. The plurality of second interconnections include a first group and a second group, and the second interconnections in the second group are electrically connected to the plurality of power reinforcing lines on the plurality of memory cell array blocks via contact plugs formed in the second insulating layer.
It is preferable that each of the plurality of power reinforcing lines is allocated to at least two first interconnections, and the pitch of the plurality of power reinforcing lines spans at least four first interconnections. It is also preferable that each of the plurality of power reinforcing lines is bent with respect to the first interconnections and at least four times over a semiconductor device, each of the plurality of power reinforcing lines is bent over a plurality of sub-word line drivers arranged on peripheral regions of the plurality of memory cell array blocks, each of the plurality of power reinforcing lines is connected to one of a plurality of sense amplifiers allocated to each of the plurality of memory cell array blocks via the plurality of second interconnections in the second group, and a normal word line enabling signal is transmitted to one of a plurality of sub-word line drivers allocated to each of the plurality of memory cell array blocks via each of the plurality of first interconnections, and a column selection signal is transmitted to one of the plurality of the sense amplifiers via the plurality of second interconnections in the first group.
In order to achieve the second objective, there is provided a semiconductor device. The device includes a plurality of memory cell array blocks, a plurality of first interconnections that extend in one direction and are spaced apart from one another on a semiconductor substrate on which the plurality of memory cell array blocks are formed, a first insulating layer for insulating the plurality of first interconnections, a plurality of power reinforcing lines that extend in one direction and are spaced apart from one another on the plurality of first interconnections on the first insulating layer, a second insulating layer for insulating the plurality of power reinforcing lines and having contact plugs, and a plurality of second interconnections that intersect the plurality of first interconnections and the p
Cho Chang-hyun
Kim Ki-nam
Lee Jae-young
Yang Won-suk
Marger & Johnson & McCollom, P.C.
Nelms David
Samsung Electronics Co,. Ltd.
Vu David
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