Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt prioritizing
Reexamination Certificate
2000-01-24
2002-10-22
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt prioritizing
C710S107000, C710S240000, C710S244000
Reexamination Certificate
active
06470407
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for arbitrating interrupt priorities among peripherals in a microprocessor-based system
BACKGROUND OF THE INVENTION
In a microprocessor-based system there are usually several peripherals connected to a central processing unit (CPU), and each peripheral must be able to communicate with the CPU at all times. To ensure that the requests originating from each peripheral can be distinguished from each other, and if simultaneous requests for access to the CPU by two or more peripherals occur, such requests are queued in a deterministic and meaningful manner. It is necessary to have a CPU interrupt arbitration logic in order to identify which peripheral, among all those that have an interrupt request which has been sent to the CPU and is accordingly pending, must be serviced by the CPU.
This arbitration logic must have the following requirements. It must be contained in the CPU and should be independent of the number and type of peripherals connected to the system so that it is not necessary to provide a custom CPU for each type of system. There should be no limit (or a very high limit) to the number of peripherals that can be connected to the same CPU. It should be possible to dynamically configure the priority of the various peripherals and to set a priority limit in the CPU so that the peripherals requesting an interrupt whose priority is lower than the set limit do not generate an actual interrupt. The arbitration logic should also use the least possible silicon area of the chip. In addition, the system should operate even when the system clock is stopped. The system clock is then activated as soon as an interrupt request from one of the peripherals connected to the CPU is detected.
In summary, if no peripheral sends an interrupt request to the CPU, the clock is stopped, but the CPU must equally be able to perform its tasks even if it does not have to service the peripherals. The above described arbitration logic, in its most simple form, is a connection of the daisy-chain type among all the peripherals. Each peripheral has an input of the daisy-chain type and a daisy-chain output. The output is active only if the input is active and the peripheral has no pending interrupt requests submitted to the CPU.
The output of one peripheral is connected to the input of the next peripheral in descending order of priority. The input of the first peripheral is connected to a logic level which is always active, and the output of the last peripheral is left floating.
FIG. 1
illustrates an arbitration logic of the daisy-chain type, in which a plurality of peripherals
1
,
2
and
3
are connected to the same CPU
4
.
Each peripheral includes an OR logic device, designated by the reference numerals
5
,
6
and
7
respectively for the peripherals
1
,
2
and
3
. As mentioned, in the first peripheral
1
the output
8
is connected to the input of the next peripheral
2
. Likewise, the output
9
of the second peripheral
2
is connected to the input of the third peripheral
3
.
The input of the first peripheral
1
, designated by the reference numeral
10
, is, in the case of
FIG. 1
, always forced to the logic value zero. Alternatively, it can always be forced to the logic value one if an opposite logic is used. The output
11
of the third peripheral
3
is, instead, always left floating.
Each peripheral further has an interrupt request input IRQ. The peripherals after the first one have an input DC which is provided by the output of the preceding peripheral. If the input IRQ is set to one, the corresponding peripheral sends an interrupt request to the CPU. Each peripheral wins if its input DC is set to zero and IRQ is set to one. Therefore, for example, if the first peripheral
1
outputs a logic value of one which is then fed to the input DC of the peripheral
2
, then the peripheral
1
wins with respect to the peripheral
2
and peripheral
3
.
The portion of the CPU
4
designated by the reference numeral
12
indicates the arbitration logic arranged within the CPU. The connection
13
indicates the connection by which the CPU communicates with the peripherals
1
,
2
and
3
.
The above-described embodiment is satisfactory with regards to the independence of the arbitration logic with respect to the number of connected peripherals, the arbitration speed of the system, and the number of peripherals that can be connected, silicon area occupation and operation with the system clock stopped. However, it is not possible to dynamically configure the priority of the various peripherals and to set a priority limit in the CPU so that peripherals requesting an interrupt with a priority below the set limit do not actually generate an interrupt.
Another approach requires the use of a priority encoder in the CPU, with an input for each peripheral. The drawback of this approach lies in determining the number of interrupt request inputs. If this number is set low, then there is a limit to the number of peripherals that can be connected to the system. Otherwise, if it is set to a high value, the requirement of the least possible silicon area consumption is not met. Finally, if the number of outputs is chosen according to the number of peripherals, then the requirement of the arbitration logic is independent of the number of peripherals that can be connected to the central processing unit is not met.
A third conventional approach is based on a serial interrupt bus to which the CPU and the peripherals with pending interrupt requests serially send their priority. The serial interrupt bus is a wired-OR connection. If many devices send conflicting logic values simultaneously, the bus assumes an active logic value.
The priorities are arranged on the bus bit by bit, starting from the most significant bit. At any time, if a peripheral detects on the bus a value which differs from the value that it is forcing on the bus, then that peripheral has lost the arbitration because another peripheral has a higher priority. The first different bit in the priority value is zero for the losing peripheral, and one for the winning peripheral. The losing peripherals do not take part in arbitrating subsequent priority bits. At the end of the arbitration, only the peripheral with the highest priority has never lost, and, is therefore, the winner. If two peripherals have the same priority, then a so-called daisy-chain connection through all the peripheral decides the final priority. Two peripherals can have the same priority if there are more peripherals than priority levels.
If the CPU takes part in the arbitration exactly like any peripheral with a pending interrupt, then the interrupts that arrive from peripherals whose priority is lower than the priority of the CPU are automatically rejected. This last approach meets the above-listed requirements, except for the fact that the system does not perform arbitration in the smallest number of clock cycles and the system does not operate when the system clock is stopped.
A number of clock cycles equal to the number of bits in the priority values must in fact elapse before it is known whether there is a pending interrupt request that must be serviced, or the CPU has instead won the arbitration with the peripherals. Therefore, before modifying the priorities it is necessary to complete the entire arbitration cycle.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for arbitrating interrupt priorities among peripherals which overcomes the drawbacks of the above described approaches, and, in particular, in which the arbitration logic is independent of the number and type of peripherals connected to the system.
Another object of the present invention is to provide a method for arbitrating interrupt priorities among peripherals in which there is no limit to the number of peripherals that can be connected to the central system.
Yet another object of the present invention is to provide a method for arbitrating interrupt priorities among peripherals in which the system performs arbitrat
Dharia Rupal
Jorgenson Lisa K.
STMicroelectronics S.r.L.
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