Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2006-09-05
2006-09-05
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
C370S910000
Reexamination Certificate
active
07103693
ABSTRACT:
A balanced approach is provided for interrupt coalescing, wherein interrupts of locking and other small size packets are maximized, while large data segment interrupts are minimized. Thus, the most desirable interrupt characteristics of both large data segments and smaller packets are achieved. Usefully, a data processing system has an adapter connecting the system to a network to receive incoming packets of varying size, the incoming packets respectively carrying messages to interrupt the system processor. Each incoming packet is analyzed, to determine whether or not it meets one or more prespecified criteria, at least a first criterion being related to the size of the incoming packet. The processor is immediately interrupted in accordance with the interrupt message carried by the analyzed packet, if the packet meets all the prespecified criteria. If the analyzed packet does not meet all of the prespecified criteria, the processor is interrupted in accordance with a specified interrupt coalescing technique.
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Anand Vaijayanthimala K.
Girouard Janice Marie
Ratliff Emily Jane
Dawkins Marilyn Smith
International Business Machines - Corporation
Ray Gopal C.
Skarsten James O.
Yee Duke W.
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