Method for analyzing component mounting board

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000

Reexamination Certificate

active

07873932

ABSTRACT:
A method for analyzing a component mounting board comprising a step (A) for forming a multilayer substrate shell model of a multilayer wiring board, a step (B) for forming a multilayer component shell model divided by element division lines based on the bonding position of a component to the surface of the multilayer wiring board, step (C) for redividing the mounting position of the component in the multilayer substrate shell model, and step (D) for forming an analysis model by bonding the neutral plane of the substrate and the neutral plane of the component through one of a beam element and a solid element, i.e. a bonding element equivalent to mounting conditions of the component, wherein precision of analysis is enhanced while reducing computation cost by performing calculation while imparting boundary conditions to the analysis model.

REFERENCES:
patent: 6753253 (2004-06-01), Takahashi et al.
patent: 7139678 (2006-11-01), Kobayashi et al.
patent: 2003/0055612 (2003-03-01), Amakai et al.
patent: 2000-304630 (2000-11-01), None
patent: 2004-013437 (2004-01-01), None
patent: 2004-227337 (2004-08-01), None
patent: 2006-53747 (2006-02-01), None

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