Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-01-29
2001-06-26
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06253359
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to methods for designing and fabricating digital circuits, and in particular to simulation of the circuit design in order to determine worst case time delays.
BACKGROUND OF THE INVENTION
Before an integrated circuit is fabricated, it is first designed by simulating the operation of the proposed circuits that are to be included within the integrated circuit. Simulation is used to verify correct functional operation of the circuit, as well as to verify correct dynamic timing operation. when two signal lines on a integrated circuit are physically adjacent there is a capacitance between the signal lines that may cause signal interference due to signal coupling.
A commonly used simulator for designing integrated circuits is SPICE, which is available from the University of California at Berkeley, via the Department of Electrical Engineering and Computer Sciences. However, a SPICE simulation of all the nets in an entire chip is far too complex to be practical.
In order to perform a SPICE simulation of a circuit, all of the nodes between every component in the circuit need to be numbered. Then those nodes, the type of components at each node, and the component magnitudes are entered into the SPICE program.
If the circuit which is being simulated is an entire integrated circuit chip, then the number of nodes and corresponding components which need to be entered into the SPICE program is overwhelming. Firstly, the number of nets may be 40,000 in a typical integrated circuit design. Secondly, for each such net, about seventy discreet components need to be entered because in the actual chip, the net components are distributed. Specifically, each signal line has capacitance which is distributed throughout the line; and each signal line also has a resistance which is distributed throughout the line. To simulate these distributed components, each signal line needs to be represented by a ladder circuit which has about two dozen nodes; with each node having a resistor to the next node, a capacitor to ground, and a capacitor to any adjacent signal line.
After all of the nodes and corresponding components for all the nets are entered into the SPICE program, the program operates to determine the voltages which occur on each node in sequential increments of time. Typically, about 1,000 increments of ten picoseconds each are needed to obtain the entire voltage waveform on a node in one net in an integrated circuit chip. To determine the voltages for just one time increment the SPICE program repetitively solves a matrix equation which is of the form [Y][V]=[l]. Here, Y is an n-x-n matrix, V is an nx1 matrix, and I is an nx1 matrix; where n is the number of nodes in the circuit. Thus, for a single victim net with twenty aggressor nets, n is (24 nodes per net)×(21 nets) or 504.
For each increment in time
1
the SPICE program makes about five iterations before it converges on a solution. This iterative process is repeated for each of the subsequent time increments.
Using a state of the art workstation, it takes about ten minutes to perform a SPICE simulation of a single circuit which has 500 nodes and for which a solution is sought for 1,000 time increments. Such a circuit represents a typical victim net with twenty aggressor nets. Consequently, to simulate a chip which has 40,000 nets would take about 400,000 minutes, or more than 270 days to complete!
Accordingly, a primary object of the present invention is to provide a method of designing circuit chips by which the above problems are overcome.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
SUMMARY OF THE INVENTION
In general, and in a form of the present invention, a method is provided for designing an integrated circuit which contains a set of signal lines in close proximity, such that capacitive coupling among the signal lines is operable to affect a delay time of a signal on a victim signal line in the set of signal lines. The method starts by creating a trail layout for the set of signal lines. A coupling capacitance parameter is assigned to the victim signal line representative of a coupling capacitance between the victim signal line and a nearby aggressor signal line from the set of signal lines. In order to compensate for additional delay time of the signal on the victim signal line due to simultaneous switching of a signal on the nearby aggressor signal line, the coupling capacitance parameters is modified. The operation of the trail layout is then simulated using the modified coupling capacitance parameters to determine a total delay time for the signal on the victim signal line. The trail layout is modified if the total delay time for the signal on the victim signal line is not an allowable delay time value.
In another form of the invention, an integrated circuit is fabricated according to the modified trial layout.
In another form of the invention, a computer system is provided which as a mass storage device that holds a design program for designing an integrated circuit according to the above described method.
In another form of the invention, a first coefficient K that is related to delay sensitivity with respect to effective drive resistance of a first type driver and associated signal trace is determined. Prior to simulating the operation of the trail layout, the coupling capacitance parameter of the victim net is modified by multiplying it by the first coefficient K.
Other embodiments of the present invention will be evident from the description and drawings.
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S/N 09/012,813 (TI docket No. TI-25311), not included.
Joardar, Kuntal, A Simple Approach to Modeling Cross-Talk in Integrated Circuits, IEEE Journal of Sold-State Circuits, vol. 29, No. 10, Oct. 1994, p. 1212+.
van Genderen, A.J., et al.; Reduced RC Models for IC Interconnections With Coupling Capacitances, IEEE 3/92, p. 132-136 (0=8186-2645-392).
Sakurai, Takayasu, Closed-form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's, IEEE Transactions on Electron Devices, vol. 40, No. 1, Jan. 1993, p. 118-124.
Cano Francisco A.
Kapoor Deepak
Savithri Nagaraj N.
Brady III W. James
Do Thuan
Laws Gerald E.
Smith Matthew
Telecky , Jr. Frederick J.
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