Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-09
2007-01-09
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10794240
ABSTRACT:
A method for analyzing and validating clock integration properties in a circuit design is disclosed. A database of timing points that are clocked cell elements of the circuit design is generated. Next, a timing point frame showing the interaction of the clocked cell elements and the non-clocked cell elements is generated. The timing point frame graphically shows the timing network properties for the cell elements of the circuit design. A clock analysis view can be generated from the timing point frame for selected timing points. In this respect, the timing point frame shows timing points that meet a prescribed criteria (e.g., same clock domain). Therefore, the clock analysis view provides a graphical representation of timing and clock interactions for the circuit design.
REFERENCES:
patent: 6173435 (2001-01-01), Dupenloup
patent: 6205572 (2001-03-01), Dupenloup
patent: 7032198 (2006-04-01), Sano et al.
patent: 2004/0128634 (2004-07-01), Johnson et al.
patent: 2004/0225978 (2004-11-01), Fan et al.
Kuang Ser-Hou
Murphy Sean Kevin
Buchanan Ingersoll & Rooney
Dinh Paul
PicoCraft Design Systems, Inc.
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