Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Patent
1996-09-26
1997-09-16
Tsai, Jey
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
148DIG106, 438725, H01L 2170, H01L 2700
Patent
active
056680422
ABSTRACT:
A method for aligning micro patterns of a semiconductor device, capable of reducing the number of dies having poor quality in the formation of patterns, thereby achieving an improvement in operation reliability of the semiconductor device. The method of the present invention utilizes the fact that even in the case of a semiconductor wafer having alignment marks damaged due to an error occurring in the formation or etching of thin films, outer mark portions of its overlay measuring marks can be observed. For several dies sampled as observation dies from the semiconductor wafer, light exposure is carried out to form photoresist film patterns under the condition that the semiconductor wafer is misaligned from the light exposure mask. Thereafter, alignment marks and inner mark portions of overlay measuring marks are formed. A misalignment angle .theta. between the semiconductor wafer and light exposure mask is also calculated. In the stepper, the degree of misalignment is then corrected based on the result of the calculation. In this state, subsequent processes are conducted for normal dies other than the observation dies. Accordingly, it is possible to reduce the number of dies which are considered as having a poor quality, thereby achieving an improvement in operation reliability of the semiconductor device.
REFERENCES:
patent: 4712016 (1987-12-01), Matsumura
patent: 5316966 (1994-05-01), Wan Der Plas et al.
patent: 5545570 (1996-08-01), Chung et al.
patent: 5545593 (1996-08-01), Watkins et al.
Hyundai Electronics Industries Co., Ltr.
Nath Gary M.
Tsai Jey
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