Method for aligning a control signal and a clock signal

Details Method for aligning a control signal and a clock signal Method for aligning a control signal and a clock signal

1997-06-25

1999-01-05

Butler, Dennis M.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711100, G06F 104

Patent

active

058570950

ABSTRACT:
An apparatus and a method are provided for delaying or skewing a control signal provided to an electronic device such as a memory device with an alignment delay, such that the overall delay associated with the alignment delay and the propagation delay associated with outputting the control signal to the electronic device substantially equals one or more integral cycles of a clock signal. As a result, the control signal received at the electronic device is substantially aligned with the clock signal. This results in synchronizing or realigning the asynchronously-generated control signal back into a synchronous environment. The apparatus and method have unique applicability when used in memory controllers and the like for handling memory accesses with one or more memory devices, in particular with memory devices having enhanced memory transfer modes or higher transfer speeds, where even a small amount of skew between a control signal and a clock signal may significantly degrade performance. A propagation delay, or delay factor, associated with outputting the control signal to the electronic device is computed based upon the process factor for the apparatus, as well as any temperature and/or voltage variations. In addition, the delay factor may be modified dynamically to account for real-time voltage and/or temperature variations.

REFERENCES:
patent: 5479647 (1995-12-01), Harness et al.
patent: 5572722 (1996-11-01), Vogley
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5692165 (1997-11-01), Jeddeloh et al.

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