Method for addressing a symbol in a memory and device for...

Details Method for addressing a symbol in a memory and device for... Method for addressing a symbol in a memory and device for...

2006-03-29

2008-12-30

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S005000

Reexamination Certificate

active

07472255

ABSTRACT:
A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories. The addressing is then done with the aid of a word address and of a bit pointer designating the start of the symbol in the word corresponding to the word address. A shift operation is performed during an operation of reading or of writing.

REFERENCES:
patent: 4833657 (1989-05-01), Tanaka
patent: 5101343 (1992-03-01), Yokouchi
patent: 2003/0126399 (2003-07-01), Troutman et al.
patent: 2003/0126402 (2003-07-01), Okano et al.
patent: 0849709 (1998-06-01), None
IBM Technical Disclosure Bulletin: “Method for Handling Unaligned Operanda That Extend Across Memory Protection Boundaries in a Microprocessor”; Apr. 1994; pp. 597-598; vol. 37, No. 04B; Armonk, NY, US.
French Search Report FR 0503242; Nov. 2, 2006.

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