Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-11-22
2010-06-29
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S774000
Reexamination Certificate
active
07747927
ABSTRACT:
A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.
REFERENCES:
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5768192 (1998-06-01), Eitan
patent: 5887145 (1999-03-01), Harari et al.
patent: 5890207 (1999-03-01), Sne et al.
patent: 5890219 (1999-03-01), Scaringella et al.
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6047361 (2000-04-01), Ingenio et al.
patent: 6216247 (2001-04-01), Creta et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6233717 (2001-05-01), Choi
patent: 6530007 (2003-03-01), Olarig et al.
patent: 6901494 (2005-05-01), Zumkehr et al.
patent: 2003/0097520 (2003-05-01), Lai et al.
patent: 2004/0049627 (2004-03-01), Piau et al.
patent: 2005/0144358 (2005-06-01), Conley et al.
patent: 2005/0144360 (2005-06-01), Bennett et al.
patent: 2005/0195653 (2005-09-01), Conley et al.
patent: 2007/0118713 (2007-05-01), Guterman et al.
patent: WO 00/67132 (2000-11-01), None
patent: WO 02/05102 (2002-01-01), None
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 11/286,100 on Sep. 21, 2007, 13 pages.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” corresponding International Patent Application No. PCT/US2006/060932, mailed on May 9, 2008, 13 pages.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 11/286,100 on Nov. 7, 2008, 15 pages.
Taiwanese Patent Office, “Office Action and Search Report,” corresponding Taiwanese Patent Application No. 095143261, mailed on Mar. 13, 2009, 8 pages.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 11/286,100 on Aug. 6, 2009, 17 pages.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 11/286,100 on Mar. 12, 2008, 9 pages.
USPTO, “Notice of Allowance and Fee(s) Due,” mailed in related U.S. Appl. No. 11/286,100 on Feb. 4, 2010, 19 pages.
Barrocas Milton Lourenco
Cedar Yoram
Conley Kevin M.
Gonzalez Carlos
Guterman Daniel C.
Chung Phung M
Davis , Wright, Tremaine, LLP
Sandisk Corporation
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