Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1998-09-03
2001-02-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S637000, C438S640000, C438S675000
Reexamination Certificate
active
06190928
ABSTRACT:
DESCRIPTION OF THE PRIOR ART
Rapidly developed progress has recently been made which allows more electronic elements such as field effect transistors to be integrated on a single chip. Consequently the metal interconnection pattern by which electronic elements are connected is more complicated. In order to meet a need of high operating speed without increasing occupied chip area of metal interconnection lines, a multi-level metallization structure, which comprises several levels of metal interconnection lines, an inter metal dielectric (IMD) layer therebetween used for isolation, and vias by which different levels can be connected, is generally employed. However, an alignment between vias and its underlying metal interconnection lines is a crucial factor for product yield and reliability. Therefore, in a practical production line, overlay specifications are made to ensure that the measured misalignment of vias, through a measuring instrument such as an OSI (overlay specification inspection) instrument, is tolerated or not. If the measured misalignment exceeds the overlay specifications, the chips should be reworked; otherwise it will result in higher contact resistivity of vias, slower operating speed, and excessively opened metal interconnection lines. Thus, an exposure process is most important in photolithography processes of vias.
Since alignment during exposure is important, an overlay mark located on a scribing line of a chip is designed to monitor alignment inside cells and is left on every layer by which an integrated circuit (IC) is constituted after finishing the sequential processes of exposure, developing and etching. A worker aligns the overlay mark of a mask to that of the proceeding layer of the chip through a microscope; however the actual misalignment inside cells is still unknown, as well as how much misalignment tolerance inside cells. In order to get more accurately aligned, the overlay specifications will be tighter so as to guarantee accurate alignment inside cells. Additionally many wafers won't proceed until a pilot run wafer is tested and its measured misalignment meets the overlay specifications in a practical production line. However, the overlay specifications are made so tight as to raise the rework rate of the pilot wafer which in turn increases idle time of an exposure tool such as a stepper, thus decreasing the throughput of production line. These problems become more serious especially in an exposure of a via so that we should find out how much process margin there is for the actual alignment inside cells in order to suitably loose the overlay specifications. Hence, it is a key issue for manufacturers to find out a method for actually measuring misalignment of via by which the throughput can be increased.
SUMMARY OF INVENTION
It is the objective of this invention to provide a method for actually measuring misalignment of via which allows for increasing the throughput of the production line.
It is another objective of this invention to provide a method for actually measuring misalignment of via which allows for decreasing rework rate of the pilot wafer and idle time of exposure tool such as a stepper.
According to the invention, a via is formed by etching an inter metal dielectric (IMD) layer using a photoresist with a via pattern as a mask so that the via pattern can be accurately transferred to the inter metal dielectric layer. Then a patterned metal interconnection line underlying the inter metal dielectric layer is etched using the patterned inter metal dielectric layer as a mask and followed by a process of striping the inter metal dielectric layer. After that, an actual misalignment can be made by measuring relative distance between the patterned metal interconnection line and the via thereon through Scanning Electron Microscopy (SEM), by which overlay specifications for OSI instrument can be verified and adjusted.
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Huang Kuan-Chieh
Li Kam-tung
Lo Yung-Tsun
Bacon & Thomas
Mosel Vitelic Incorporated
Niebling John F.
Stevenson André
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