Method for achieving very high bandwidth between the levels...

Static information storage and retrieval – Systems using particular element

Reexamination Certificate

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C711S122000, C711S141000

Reexamination Certificate

active

07986543

ABSTRACT:
A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.

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Kimura, M., “Bridging the Gap Between Packages and Chips: 10MUM Super Sonnect Technology.”, Solid State Technology, Pennwell Corporation, Tulsa OK, US, vol. 43, No. 11, Nov. 1, 2000, pp. 56, 58, 60.
International Search Report dated Nov. 6, 2008.

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