Abrading – Precision device or process - or with condition responsive... – With indicating
Reexamination Certificate
2001-09-25
2003-08-19
Eley, Timothy V. (Department: 3724)
Abrading
Precision device or process - or with condition responsive...
With indicating
C451S021000, C451S041000, C451S056000, C451S072000
Reexamination Certificate
active
06607423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor wafer fabrication, and more particularly to a system and method for selectively conditioning a surface of a polishing pad of a chemical-mechanical polishing (“CMP”) apparatus in order to achieve a desired surface profile of a semiconductor wafer subsequently subjected to CMP using the CMP apparatus.
2. Description of Related Art
During a wafer fabrication process, multiple integrated circuits are formed upon frontside surfaces of each of several semiconductor wafers processed as a group or lot. Each integrated circuit consists of electronic devices electrically coupled by conductive traces called interconnects. Interconnects are patterned from conductive layers formed on the surface of a semiconductor wafer. The ability to form stacked layers of interconnects has allowed more complex circuits to be implemented in and on relatively small surface areas of semiconductor substrates. The individual interconnect levels of multilevel interconnect structures are separated by layers of electrically insulating materials (i.e., interlevel dielectric layers).
As the number of interconnect levels is increased, the stacking of additional interconnect layers on top of one another tends to increase the elevational disparities in frontside surface topographies. Problems arise when attempting to form interconnects upon rugged frontside surface topographies. Abrupt elevational changes in the frontside surface topography of a semiconductor wafer typically occur at or near lateral edges of underlying patterned features, e.g., interconnects. The tendency of layers formed upon the surface topography of a semiconductor wafer to be thinner over such abrupt elevations changes (i.e., “steps”) is referred to as the “step coverage” problem. In additional to the step coverage problem, large and abrupt elevation disparities lead to depth of focus problems. Depth of focus problems become an issue during the lithographic process in which layers are patterned across a semiconductor topography. A major factor in the processing of integrated circuits with submicron device dimensions is the limited depth of focus of the optical steppers used to pattern circuit features. In order to obtain maximum resolutions, imaging surfaces must be fairly planar with a suitable elevational disparity less than about 0.5 microns. Accordingly, interlevel dielectric planarization techniques must be employed in order to make imaging surfaces substantially planar.
Chemical-mechanical polishing/planarization (“CMP”) is a popular method of planarizing the upper surface of a layer (e.g., a dielectric or conductive layer) formed upon the frontside surface of a semiconductor wafer. CMP combines chemical etching and mechanical buffing to remove raised features upon the frontside surface of the semiconductor wafer.
FIGS. 1 and 2
will now be used to describe an exemplary CMP apparatus.
FIG. 1
is a top plan view of the exemplary CMP apparatus
10
, and
FIG. 2
is a side elevation view of exemplary CMP apparatus
10
. CMP apparatus
10
is representative of, for example, a model Auriga or CMP-V polisher made by SpeedFam International, Inc. (Chandler, Ariz.). CMP apparatus
10
includes a platen (i.e., rotatable table)
12
, a polishing pad
14
, a wafer carrier or “chuck”
16
, and a slurry delivery system
18
.
As shown in
FIG. 2
, polishing pad
14
may include two separate disk-shaped polishing pads
14
a
and
14
b
stacked vertically upon one another. An underside surface of a first polishing pad
14
a
may be attached (e.g., adhesively) to a substantially planar upper surface of platen
12
. A second polishing pad
14
b
may be attached (e.g., adhesively) to an upper surface of polishing pad
14
a
. Polishing pad
14
a
may be made of, for example, a rigid, microporous polyurethane material (e.g., a model IC1000 polishing pad made by Rodel, Newark, Del.). Polishing pad
14
b
may be made of, for example, a polyurethane-impregnated polyester felt material (e.g., a model Suba IV polishing pad made by Rodel).
Polishing pads
14
a
and
14
b
have outer diameters “O.D.”, and may be stacked as shown in
FIG. 2
such that their outer diameters are vertically aligned. As shown in
FIG. 2
, polishing pad
14
b
has a hole in the center, and accordingly has an inner diameter “I.D.”. Polishing pad
14
b
also has a center line “C” midway between outer diameter “O.D.” and inner diameter “I.D.” as shown in FIG.
2
.
During operation of exemplary CMP apparatus
10
, a semiconductor wafer
20
is placed within wafer chuck
16
. Platen
12
is set into rotational motion about a rotational axis
22
normal to the substantially planar surface. Wafer chuck
16
is set into rotational motion about a rotational axis
24
. A force “F” is applied between wafer chuck
16
and platen
12
as shown in
FIG. 2
, pressing a frontside surface of semiconductor wafer
20
against the rotating upper surface of polishing pad
14
(i.e., polishing pad
14
b
). Slurry delivery system
18
delivers a liquid slurry to polishing pad
14
, saturating polishing pad
14
with the liquid slurry. The liquid slurry may contain, for example, abrasive particles and a mild etchant chemical which softens or catalyzes the exposed material at the frontside surface of semiconductor wafer
20
. Elevationally extending portions of the frontside surface of semiconductor wafer
20
are removed by combined chemical softening of the exposed surface material and physical abrasion brought about by relative movement between polishing pad
14
and the frontside surface of semiconductor wafer
20
.
When used to planarize a semiconductor wafer surface, CMP apparatus
10
has two important performance factors: (i) polishing removal rate, and (ii) resultant semiconductor wafer surface planarity or “uniformity”. A high polishing rate is desirable in order to maximize the number of wafers which may be planarized in a given amount of time. A high measure of resultant semiconductor wafer surface planarity or “uniformity” is also desirable in order to reduce the step coverage and depth of focus problems described above.
The polishing rate performance of CMP apparatus
10
becomes degraded as waste materials build up on the upper surface of polishing pad
14
(i.e., polishing pad
14
b
) during use. The waste materials smooth out the textured upper surface of the pad, reducing the effectiveness of polishing pad
14
. In order to maintain the effectiveness of polishing pad
14
, the upper surface of polishing pad
14
is typically renewed periodically using a conditioning operation.
FIG. 3
is a side elevation view of CMP apparatus
10
wherein polishing pad
14
is undergoing an exemplary conditioning operation. The conditioning operation employs a pad conditioner
26
having a substantially planar abrasive surface
28
. Abrasive surface
28
may include abrasive particles (e.g., diamond particles) embedded therein. During conditioning, platen
12
is set into rotational motion about rotational axis
22
, and pad conditioner
26
is set into rotational motion about a rotational axis
30
normal to substantially planar abrasive surface
28
. Abrasive surface
28
of pad conditioner
26
is brought into contact with the upper surface of polishing pad
14
(i.e., polishing pad
14
b
). As a result, a portion of the upper surface of polishing pad
14
is abraded (i.e., removed), along with any waste materials built up on the upper surface of polishing pad
14
.
The semiconductor wafer surface planarizing or “uniformity” performance of CMP apparatus
10
is dependent upon the planarity of the upper surface of polishing pad
14
. Past efforts to assess the uniformity performance of CMP apparatus
10
following the conditioning of polishing pad
14
include using CMP apparatus
10
to polish a surface of one or more “qualification” wafers. Thicknesses of one or more layers formed upon the surfaces of the qualification wafers are then measured at various locations about the surfaces in order to determine the surfac
Arcayan Rigel G.
Burleson Michael K.
Pineda-Garcia Jose M.
Advanced Micro Devices , Inc.
Eley Timothy V.
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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