Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-06-04
2000-06-20
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711169, 711170, 36523006, 713400, G06F 1300
Patent
active
060790016
ABSTRACT:
Accordingly, the present invention provides a method for synchronously accessing memory in order to improve the performance in systems which use memories with slower cores. A first address for a first memory access is provided during a first clock period. A first control signal to indicate an address phase of the first memory access is activated during the first clock period. A second control signal to indicate a data phase of the first memory access is activated during a second clock period subsequent to the first clock period. A first data element accessed by the first address is received during a third clock period immediately subsequent to the second clock period. A second address for a second memory access is provided during the third clock period. The first control signal indicating an address phase of the second memory access is activated during the third clock period.
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Le Chinh H.
Vauk, Jr. Gerald E.
Chan Eddie P.
Kim Hong
Motorola Inc.
Polansky Paul J.
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