Method for accessing memory by activating a programmable chip se

Details Method for accessing memory by activating a programmable chip se Method for accessing memory by activating a programmable chip se

1996-06-06

1998-09-22

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

365233, 395855, G06F 1200, G11C 800

Patent

active

058130411

ABSTRACT:
A data processing system (20) having a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match. Continued assertion reduces access time to an external device allowing the user to determine the trade-off between high speed access and low power consumption. Additionally, a speculative burst access is made without regard to match criteria, allowing a device to prepare for access while data processor (22) determines the next device to access. Here a load burst address (LBA) signal is speculatively provided to an activated device, and where the next access is to another device, the speculative access is aborted.

REFERENCES:
patent: 4816997 (1989-03-01), Scales, III et al.
patent: 5151986 (1992-09-01), Langan et al.
patent: 5448744 (1995-09-01), Eifert et al.
patent: 5502835 (1996-03-01), Le et al.

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