Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2000-12-29
2004-10-05
Elamin, A. (Department: 2116)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S300000, C713S310000, C713S320000, C713S323000, C713S324000
Reexamination Certificate
active
06802015
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a computer system that includes a central processing unit that can operate at different frequencies. More particularly, the present invention relates to a portable computer system in which the speed of the central processing unit is accelerated in response to system command entries from a user.
2. Background of the Invention
Power management is an integral part of a battery-operated portable notebook computer. To maximize battery life, computer systems manage the power drain on the batteries by placing the computer system in a low power mode whenever possible. Typically, a computer system is placed in a low power mode when the computer system is inactive. The computer system is subsequently awoken in response to system activity, such as occurs when the user depresses any key on the keyboard or moves or presses a button on a mouse. See U.S. Pat. No. 5,218,704. Thus, any keystroke forms a break event that wakes the system from an idle mode.
Computer systems typically include input devices, such as a keyboard and a pointing device. The keyboard usually includes 101 alphanumeric, positioning, and function keys. A mouse or other pointing device includes some form of motion sensor, and 2 or 3 finger operated control buttons. The keyboard and pointing device connect electrically to a keyboard controller via a PS/2 bus, which is a four wire, synchronous bus. The keyboard controller typically comprises a microprocessor-based controller, such as the Intel 8042 or Intel 8051. When a key is pressed, logic inside the keyboard issues a “make code” signal to the keyboard controller. A “break code” is issued when the key is lifted. Multiple keys may be pressed, especially in combination with a “shift”, “Ctrl”, “Alt”, or “function” key. The keyboard controller identifies the “make” code and translates it to a “scan code” that is used by the operating system and application software. A mouse periodically issues a three byte packet of information. The first byte identifies if a button is pressed, and if so, which byte is pressed. The second and third bytes identify the displacement of the mouse along the X and Y axis that has occurred since the last mouse packet was sent, usually in two's complement format.
After a key press on the keyboard or mouse, or after a mouse movement, the keyboard controller generates a standard interrupt signal to the core chipset. Typically an IRQ
1
is transmitted in response to a keyboard event, and IRQ
12
is transmitted in response to a mouse event. The system BIOS responds to the keyboard interrupt (IRQ
1
), and assembles the scan codes for the operating system software to use. The mouse interrupts (IRQ
12
) are transmitted directly to the operating system software driver. In the Microsoft Windows Operating System, an input device driver examines the scan code and mouse data. The operating system will either message data as virtual scan codes to the application software, or will use the input data for its direct system commands.
The core chipset may include some limited power management functionality that permits the system to be placed in a low power state when the system is inactive. The system typically monitors inputs from the keyboard or mouse to determine when the system should break from the low power mode. The problem, however, is that placing the computer in a low power mode inevitably compromises system performance. A system in a low power state is not immediately responsive to user demands, and thus a user experiences some period of latency as the computer resumes its normal operational state. As the latency period becomes longer, it becomes increasingly irritating to the user.
Developing a power management system that is instantly and accurately responsive to user demands is problematic. There are two general techniques that have been used and discussed over the years for managing power in a portable computer. The first technique involves the manipulation of the operating frequency of the CPU and/or chipset. In particular, the system clock speeds are lowered to save power during periods when the system is perceived to be idle. See U.S. Pat. Nos. 5,625,826 and 5,504,908.
The manipulation of clock frequency for power management fell out of favor with the advent of techniques that completely halted the CPU by stopping the CPU clock. One technique that gained acceptance was to have the South bridge device generate a Stopclock signal to the CPU that caused the system to turn off the CPU clock, thereby placing the CPU in a suspended state. The Stopclock signal was generated in response to some event, or some indication that the system was inactive. A variation of the Stopclock technique permitted the system to resume normal operation for a fixed period to respond to a particular system event, followed by returning to the idle mode. This was commonly referred to as a Burst event. Another technique that was developed was halting the CPU in response to a software Autohalt command. The Autohalt technique required support of the application or operating system, which was supposed to report when it had finished a routine, and then instruct the CPU to go into a low power state. While both Stopclock and Autohalt have relatively minimal latency periods, they are not the most efficient techniques to control the CPU frequency, because the CPU must either be started or stopped, and cannot be throttled to slower or faster speeds. The ability to throttle the CPU to slower speeds also has the advantage of being able to lower the voltage to the CPU, while the CPU remains operational, albeit at a lower speed. Also, the Stopclock technique generally does not impact the amount of power drawn by the chipset.
Because of these limitations, power management in current portable computers has returned to the use of frequency manipulation to conserve battery power. Most CPU manufacturers now offer a frequency manipulation technique as part of current processors. For example, Intel has a technology that it markets as “Speedstep®” that enables the processor to operate at different clock speeds. Similarly, AMD has the “PowerNow!®” technology that also implements frequency manipulation of the CPU clock speed. Likewise, Transmeta® has the “LongRun®” technology that also performs frequency manipulation. Each of these techniques relies on lowering the CPU core frequency and/or chipset in response to either a system power state, a manual setting by the user, or the actual usage of the system.
As an example, the PowerNow! Technique from AMD senses the system idle time by looking at the excess capacity of the CPU. Thus, for example, if the CPU is idle greater than 20% of the time, the system can automatically lower the system clocks to 80% of their maximum clock frequency (i.e., from 600 MHz to 500 MHz. This enables the system to continue operating, but draw less power. In addition, frequency control circuitry for most manufacturers also typically includes a voltage control circuit that selects a lower CPU operating voltage level when the slower speed operating frequency is used.
Although these frequency manipulation techniques have improved the efficiency of the CPU in portable computer systems, the decision regarding when to change frequency still is archaic. Almost all systems are reactive, and thus wait to change speed until after the speed change is required. Very few (if any) systems exist that attempt to predict the performance requirement of the CPU, so as to modify the CPU clock speed at the very time that the change in speed is needed. Instead, the most advanced technique looks at an average of system idle times to determine what the current speed setting should be for the CPU. Such as system cannot efficiently match peak demands of a computer system.
One implementation suggested by the assignee of the present invention in U.S. Pat. No. 5
Elamin A.
Trujillo James K.
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