Method for absolute address history table synonym resolution

Details Method for absolute address history table synonym resolution Method for absolute address history table synonym resolution

1998-04-30

2000-10-24

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711221, 711213, G06F 1210

Patent

active

061382159

ABSTRACT:
A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which prevents any sort of full or large partial adds of ranges of base, index, or displacement has two index values generated and two AAHT arrays, one each for instruction and operand logical requests. It handles cases in which the data is not directly from the GPR array. For designs that aim at improving performance data for some operations that update GPR's may be used for address generation prior to the execution and write to the GPR array, these include data bypass for Load Address (LA) and Load (L). The system handles instruction fetches, relative branches, other special instruction address instruction fetch requests, and those started as a result of a branch history table (BHT) predicted instruction fetch. A method for AAHT synonym resolution improves the accuracy of the index value for an Absolute Address History Table buffer.

REFERENCES:
patent: 5148538 (1992-09-01), Celtruda et al.
"A High-Frequency Custom CMOS S/390 Microprocessor" by Webb et al., IBM Journal of Research and Development, vol. 41, No. 4/5, Jul./Sep. 1997, pp. 463-473.
"Effecting A One-Cycle Cache Access In A Pipeline Having Combined D/A Using A BLAT" IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan. 1989, by Rechtschaffen et al., pp. 12-13.
"Mechanism For Acceleration Of Cache References" by Pomerene et al., IBM Technical Disclosure Bulletin, vol. 25, No. 3B, Aug. 1982, pp. 1740-1745.
IBM Technical Disclosure Bulletin, vol. 36, No. 1, Jan. 1993, entitled Handling Address Generate Interlocked Distribution Without Message Delay, pp. 335-337.

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