Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2008-07-01
2008-07-01
Phan, Raymond N (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S110000, C710S269000
Reexamination Certificate
active
07395362
ABSTRACT:
A computer system, more generally a master-slave system, may be configured with interrupt handling capability without additional dedicated interrupt lines. An interrupt condition may be bound with its relevant cause information and transmitted by a slave device during a typical response to any operation that a master device may have issued, such as a read or a write. In addition, a link level protocol may be configured in the bus interface of the master device to continually poll specified addresses, or to issue a unique command targeted at interrupts. The master device may be unaware of the unique requests, as the bus may remain idle as seen by the master device. The response to the unique requests may be similar to the interrupt message information transmitted as part of a response to a standard request that may be made by the master device. A master device may thus also receive interrupts without having to configure a slave device with the ability to make requests, or without the master device having to poll for interrupts.
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Drexler Barry L.
Sipek Steven J.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Phan Raymond N
Standard Microsystems Corporation
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