Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-12-07
2001-04-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S651000, C257S344000
Reexamination Certificate
active
06214710
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and more particularly to a semiconductor device having reduced contact resistance and leakage and method of construction.
BACKGROUND OF THE INVENTION
Semiconductor device fabrication often utilizes a salicide process. A salicide process is a self-aligned silicidation process. In a silicidation process, a metal, such as titanium, is placed into contact with silicon and heated. Heating of the titanium and silicon causes the silicon and titanium to combine to form a silicide compound. Silicidation is conventionally used to provide a conductive contact between silicon in a semiconductor device and a metal contact, which may be connected to a conductive lead. The resulting silicon-silicide-metal combination provides less contact resistance than provided with a direct metal-to-silicon contact. Large contact resistance is generally detrimental to the performance of a semiconductor device. A silicidation process is self-aligned, or a salicide process, when masking is not required to deposit the metal used to form the silicide compound.
A problem with the use of titanium in a silicide compound is that titanium silicide suffers from size effects. As the volume of a titanium silicide region in a semiconductor device decreases, its contact resistance increases. Thus, as semiconductor devices shrink, particularly the length of a gate in a semiconductor device, the use of titanium silicide may become unacceptable due to resulting high contact resistances. Because of the susceptibility to size effects of titanium silicide, cobalt and nickel are sometimes used as alternatives. In contrast to titanium silicide, cobalt silicide and nickel silicide do not suffer size effects and have a relatively constant resistance for varying volumes of the resulting silicide compound.
Although the use of cobalt or nickel in a silicidation process offers benefits over the use of titanium, their use is not without disadvantages. For example, the use of cobalt or nickel can result in current leakage into the silicon substrate. Such current leakage can be detrimental. In addition, the use of cobalt or nickel, although providing relatively constant contact resistance for varying volumes of silicide, has resulted in greater than expected contact resistances.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a semiconductor device having reduced contact resistance and low leakage and method of construction for such a device. The present invention recognizes that current leakage arising from the use of cobalt or nickel in a silicidation process may be attributed to spiking of either cobalt or nickel into the silicon substrate. The present invention also recognizes that such spiking may be attributed to a rough interface between the cobalt silicide or the nickel silicide and the silicon substrate in a silicide process. The present invention additionally recognizes that the higher than expected contact resistances resulting from the use of either cobalt or nickel in the silicide process may be attributed to native oxide residing on the surface of the formed silicide. Such native oxide results in degradation of the contact formed in the silicide process. Such degradation results in higher than expected contact resistance.
The present invention provides a semiconductor device and method of construction that addresses shortcomings of prior devices and methods. According to one aspect of the invention, a method for constructing a semiconductor device includes separating a semiconductor gate body from the outer surface of the substrate by a gate insulator layer, forming a conductive drain region in the outer surface of the substrate and spaced apart from the gate conductor body, and forming a conductive source region in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The method also includes depositing a metal buffer layer over the conductive source region and conductive drain region, depositing a metal layer over the metal buffer layer, and reacting the metal layer and metal buffer layer with the conductive source region and conductive drain region to form respective first and second silicide regions.
According to another aspect of the invention, a semiconductor device includes a semiconductor gate body separated from the outer surface of the substrate by a gate insulator layer, a conductive drain region formed in the outer surface of the substrate and spaced apart from the gate conductor body, and a conductive source region formed in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The semiconductor device also includes a first silicide region overlying the conductive drain region, a second silicide region overlying the conductive source region. The first and second silicide regions comprise a silicide selected from the group consisting of CoZr
y
Si
x
, CoHf
y
Si
x
, NiZr
y
Si
x
, and NiHf
y
Si
x
, where “y” is less than one.
The invention provides several technical advantages. For example, one embodiment of the invention provides a method for constructing a semiconductor device that results in a device having reduced contact resistance and low leakage but that incorporates advantages associated with the use of cobalt or nickel to form silicide regions overlying portions of the semiconductor device. Such advantages include a relatively constant contact resistance for varying gate lengths, which is particularly important as device sizes shrink.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
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patent: 5047367 (1991-09-01), Wei et al.
patent: 5567652 (1996-10-01), Nishio
patent: 5888888 (1999-03-01), Talwar et al.
patent: 6020239 (2000-02-01), Gambino et al.
patent: 6037254 (2000-03-01), Hong
patent: 6046113 (2000-04-01), Hong et al.
patent: 6114733 (2000-09-01), Hong
Cho Chih-Chen
Hwang Ming Jang
Park Kyung-Ho
Brady III Wade James
Dang Phuc T.
Denker David
Nelms David
Telecky , Jr. Frederick J.
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