Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1999-03-25
2001-01-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S586000, C438S199000
Reexamination Certificate
active
06174791
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for a pre-amorphization. More particularly, the present invention relates to a method for creating an amorphous layer over the gate and the source/drain regions of a MOS transistor before performing a self-aligned titanium silicide process (Salicide process).
2. Description of Related Art
As the dimensions of polysilicon gate continue to shrink, narrow line effect becomes a major factor in producing high-quality, self-aligned titanium silicide layers. The so-called narrow line effect refers to problems due to a reduction in gate dimensions. With a small gate dimensions, too much stress may accumulate at the interface between the polysilicon gate and the metal silicide layer. In addition, there may be too few nucleation sites on the original surface for forming a high quality metal silicide layer, thereby leading to an increase in sheet resistant that may frequently affect the operation of the transistor gate.
Therefore, in the fabrication of semiconductor devices having a line width smaller than 0.25 &mgr;m, a pre-amorphization implant (PAI) is normally carried out first. The PAI creates a layer of amorphous silicon over the polysilicon gate and the source/drain regions of a transistor so that a subsequent self-aligned silicide process can produce a metal silicide layer having a lower sheet resistant.
The most common pre-amorphization method includes bombarding the surface of a polysilicon layer with arsenic (As
+
) ions. The arsenic ions damage the internal crystal structure of the polysilicon layer so that a layer of amorphous silicon is formed. However, after a PAI treatment with arsenic ions, some of the ions may pass through the grain boundaries of the polysilicon crystal and finally end up at the interface between the polysilicon gate or the gate oxide layer itself. In some cases, the arsenic ions may even penetrate into the substrate leading to an increase in subthreshold current of an NMOS and the amplification of the kink effect.
In addition, if the transistor is a PMOS, P-type dopants are embedded inside its source/drain regions. Therefore, whenever a pre-amorphization treatment is performed with N-type arsenic ions, some of the N-type arsenic ions implanted into the source/drain regions may neutralize the effect produced by the original P-type dopants. Consequently, conductivity at the source/drain regions of a PMOS may worsen and the current (Id) flowing from the source/drain terminal may drop.
In light of the foregoing, there is a need to provide a better pre-amorphization method.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method for a pre-amorphization capable of preventing arsenic ions from penetrating through the gate polysilicon layer into the gate oxide layer, and hence reducing abnormal subthreshold current of an NMOS and kink effect.
In another aspect, the purpose of the present invention is to provide a method for a pre-amorphization capable of preventing a drop in current flowing from source/drain terminals due to performing a pre-amorphizing implant with respect to a PMOS transistor using arsenic ions.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for a pre-amorphization. The method includes the steps of forming a patterned mask layer over a substrate having PMOS transistors and NMOS transistors. The patterned mask layer has an opening that exposes the gate polysilicon layer of the NMOS transistors. Next, an inactive ion implant is carried out, implanting inactive ions into the gate polysilicon layer of the NMOS transistors using the patterned mask layer as a mask. Thereafter, a first heavy bombardment of the gate polysilicon layer with ions is carried out, again using the patterned mask layer as a mask. After that, the patterned mask layer is removed. Finally, a second heavy bombardment of the gate polysilicon layer and the source/drain regions with ions is carried out.
In the inactive ion implant, inactive ions such as nitrogen ions (N
2
+
) are implanted into the gate polysilicon layer at an energy level of between 10 KeV and 30 KeV and a dosage of between IE13 and IE15 atoms/cm
2
.
In the first heavy bombardment of the gate polysilicon layer to form an amorphous layer, arsenic ions (As
+
), for example, are implanted at an energy level of between 20 KeV and 40 KeV and a dosage of between IE14 and IE15 atoms/cm
2
.
In the second heavy bombardment of the gate polysilicon layer and the source/drain regions to form an amorphous layer, ions such as arsenic ions (As
+
) are implanted at an energy level of between 20 KeV and 40 KeV and a dosage of between IE13 and IE14 atoms/cm
2
.
Because inactive ions are first implanted into the gate polysilicon layer first, it is very difficult for arsenic ions to penetrate through the gate polysilicon layer into the gate oxide layer during the first and the second ion implant.
According to one preferred embodiment of this invention, an amorphous layer having a thickness of between 50 Å and 100 Å is formed on the surface of the gate polysilicon layer after the first heavy bombardment with ions. The nitrogen ions implanted in the inactive ion implant operation are capable of blocking the arsenic ions from passing through the polysilicon layer into the gate oxide layer. During the second heavy bombardment, the amorphous layer on the gate polysilicon layer thickens to between 200 Å and 500 Å. Because a thin amorphous layer already exists before the second heavy bombardment, ions implanted into the gate polysilicon layer in the second implant cannot penetrate through the interface between the gate polysilicon layer and the gate oxide layer interface. Since none of the ions is able to get to the substrate, subthreshold current does not increase. Therefore, subthreshold kink effect can be avoided.
Furthermore, the source/drain regions are covered by a mask layer during the first heavy bombarding operation. Since ions are added to the source/drain regions only in the second bombarding operation, concentration of the implanted ions is only moderate. Hence, the conductivity at the source/drain region decreases just a little and the current (Id) flowing from the source/drain terminals does not drop too much.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5888888 (1999-03-01), Talwar et al.
Yu et al., CMOS Transistor Reliability and Performance Impacted by Gate Microstructure, pp. 35-41, (IEEE), 1997.
Chou Jih-Wen
Hsue C. C.
Lin Tony
Bowers Charles
Hawranek Scott J.
Hickman Coleman & Hughes LLP
United Microelectronics Corp.
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