Radiant energy – Inspection of solids or liquids by charged particles – Methods
Reexamination Certificate
2002-07-08
2004-01-27
Anderson, Bruce (Department: 2881)
Radiant energy
Inspection of solids or liquids by charged particles
Methods
C250S311000
Reexamination Certificate
active
06683304
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of failure analysis in semiconductor manufacturing. Specifically, the present invention relates to the field of transmission electron microscopy sample preparation for failure analysis in semiconductor manufacturing.
2. Related Art
Failure analysis and sample preparation is an important tool in providing a detailed inspection of the physical characteristics of an integrated circuit (IC) fabricated on a semiconductor chip (IC chip). With the structure of integrated circuits decreasing in size and becoming more complex, transmission electron microscopy has emerged as a critical tool for highly site-specific failure analysis. More particularly, an important issue is the analysis of via and contact failure between layers in an integrated circuit. That is, contact and via failure analysis is one of the most common inspections in semiconductor manufacturing.
Physical characteristics of via and contact plugs provide critical factors in determining the overall performance of an IC chip. These physical characteristics are directly linked to the properties related to electrical conductivity of the via and contact plug. The most critical factors for via and contact properties include barrier metal layer coverage and plug critical dimensions, hereinafter referred to as “CD”.
Conventional transmission electron microscopy, hereinafter referred to as “TEM”, sample preparation techniques cut along the longitudinal axis of a via or contact using a focused ion beam, hereinafter referred to as “FIB”. This TEM inspection along or parallel to the longitudinal axis is the most widely used method to evaluate via and contact characteristics.
FIG. 1
illustrates the conventional TEM sample preparation technique used for cutting along the longitudinal axis with an FIB in the prior art. The IC chip
110
is placed on a sample holder
130
. The sample holder
130
is suitable for interfacing with an FIB sample holder (not shown) in order to orient the sample for cutting with the FIB.
Continuing with
FIG. 1
, the IC chip
110
is oriented such that the top layer of the IC chip
110
is exposed to the FIB
120
. The FIB
120
is perpendicular to the top and all underlying layers of the IC chip
110
in FIG.
1
. Electrical conduits, such as vias and contacts, provide electrical conduction paths between layers in the IC chip
110
. As such, the FIB
120
cuts down through the IC chip
110
parallel to the longitudinal axis of a via or contact plug. By proper displacement of the FIB, a TEM sample membrane suitable for TEM failure analysis can be prepared for examining the critical dimensions of the via or contact plug.
However, the difficulties associated with cutting to the plug center using conventional techniques make measurement of the barrier thickness and the plug's critical dimensions inaccurate. Accuracy of these measurements is affected both by the thickness of the TEM sample and the diminution of the via and contact plugs in order to build smaller IC chips.
For example, the thickness of the TEM sample makes cutting to the center of the plug impossible. A TEM sample cut parallel to the longitudinal axis creates a rectangular cross-sectional view of the plug that does not include a view of the center cross-section of the plug. This is because the TEM sample has a measurable thickness.
The center cross-section plug is a plane that includes the longitudinal axis. This center cross-section gives the best view of the plug for TEM analysis. However, the thickness of the TEM sample has an adverse affect when dealing with the decreasing physical dimensions of the contact or via plugs. In some cases, the TEM sample thickness is up to two-thirds of that of the center diameter of the plug. An adequate TEM sample showing the center cross-section of the plug is difficult to prepare using conventional techniques because of the thickness of the ion beam. Further, measurement of the critical dimensions from a TEM sample, that does not show the center cross-section plug, is difficult.
Additionally, the shielding effect due to the sample thickness and circular shape of the plug has an adverse affect when measuring the thickness of the barrier liner walls. A resulting TEM sample cut using an FIB is not uniform due to the curvature of the plug walls. This non-uniformity along with the thickness of the TEM sample introduces shielding or shadowing effects. The shadowing effect is more pronounced the further the FIB cut is made away from the center of the plug. Measurement of the barrier thickness under TEM analysis is impossible with pronounced shadowing or shielding effects.
Thus, a need exists for a preparation technique that provides better via and contact characterization for failure analysis. A further need exists for a preparation technique that provides for more accurate measurement of the physical dimensions of the via and contact plugs.
SUMMARY OF THE INVENTION
The present invention provides a method for providing transmission electron microscopy sample preparation of an integrated circuit prepared on a semiconductor chip wherein the method provides better via and contact characterization for failure analysis. Also, the present invention provides a method that achieves the above accomplishment and which also provides for more accurate measurement of the physical dimensions of the via and contact plugs.
Specifically, the present invention discloses a method for preparing a transmission electron microscopy (TEM) sample for contact and via characterization. One embodiment of the present invention discloses a method where an integrated circuit semiconductor chip, e.g., IC chip, is bonded to a piece of glass and attached to a sample holder. Areas of the IC chip are removed by polishing until a region surrounding a particular contact or via is exposed. The piece of glass supports the IC chip during the polishing process. The IC chip is cut using a focused ion beam (FIB) to create a thin membrane suitable for TEM analysis. The thin TEM sample membrane includes a plan-view cross-section from the particular contact or via. The cross-sectional plan-view is perpendicular to the longitudinal axis of the contact or via.
In another embodiment, the present invention provides a method for preparing a TEM sample membrane that includes multiple contacts or vias. The thin membrane of the TEM sample includes plan-view cross-sections of each of the multiple contacts or vias contained within the TEM sample. Each of the plan-view cross-sections is perpendicular to the longitudinal axis for each contact or via in the thin membrane suitable for TEM analysis.
REFERENCES:
patent: 5977543 (1999-11-01), Ihn et al.
patent: 6042736 (2000-03-01), Chung
patent: 6194720 (2001-02-01), Li et al.
patent: 6300631 (2001-10-01), Shofner
patent: 6496559 (2002-12-01), Morken
patent: 6497194 (2002-12-01), Libby et al.
Er Eddie
Foong Tee Siam
Jiyan Dai
Lam Tai Chui
Redkar Shailesh
Anderson Bruce
Chartered Semiconductor Manufacturing Limited
Smith II Johnnie L
LandOfFree
Method for a plan-view transmission electron microscopy... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for a plan-view transmission electron microscopy..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for a plan-view transmission electron microscopy... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3204375