Method directed to the manufacture of an SOI device

Details Method directed to the manufacture of an SOI device Method directed to the manufacture of an SOI device

2000-01-31

2001-08-07

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S149000, C438S163000, C438S165000, C438S151000

Reexamination Certificate

active

06271065

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an SOI structure including a mesa-isolation transistor, and a method of manufacturing the device.
2. Description of the Background Art
In a semiconductor device having an SOI structure, a structure is known in which a side wall is formed on a side surface of an SOI layer as an active region to mesa-isolate the SOI layer (See, for example, Japanese Patent Laid-open No. 60-258957.)
FIG. 30
is a cross section taken along a gate length of a mesa-isolation MOS transistor having an SOI structure in a conventional semiconductor device, which includes a structure shown in Japanese Patent Laid-open No. Sho 60-258957.
Referring to
FIG. 30
, the mesa-isolation MOS transistor comprises a silicon substrate
101
, a buried oxide film
102
formed on the upper surface of the silicon substrate
101
, a mesa-isolation SOI layer
103
formed on the buried oxide film
102
, and N-type high-concentration impurity regions
119
, N-type low-concentration impurity region
117
, a channel region
123
formed in the SOI layer
103
and N-type source/drain regions
121
constituting an N-channel transistor. The N-type low-concentration impurity regions
117
and the N-type high-concentration impurity regions
119
adjacent to the N-type low concentration impurity regions
117
formed respectively on the opposite sides of the channel region
123
constitute N-type source/drain regions
121
. Similarly, P-type source/drain regions
122
, each including a P-type high-concentration impurity region
120
and a P-type low-concentration impurity region
118
, and a channel region
124
are formed in the other SOI layer
103
constituting a P-channel transistor.
A gate electrode
110
is formed over each channel region
123
,
124
with a gate insulating film
104
b
therebetween, and a sidewall
111
of an insulating material is formed by deposition on a side surface of the gate electrode
110
. A P-type high-concentration impurity region
107
is formed in each N-type high concentration impurity region
119
at its end portion, and an oxide film
109
is formed on a side surface of the SOI layer
103
. Further, a sidewall
108
of an oxide film is formed on a side surface of the oxide film
109
of each N-type high concentration impurity region
119
. A plurality of wirings
113
b
of aluminum, or the like patterned on the interlayer insulating film
112
are respectively connected to the N-type and P-type source/drain regions
121
and
122
via contacts
113
a
through the interlayer insulating film.
FIG. 31
is a top plan view of the semiconductor device shown in FIG.
30
.
FIG. 30
is a cross section taken along the line A—A in
FIG. 31
, and
FIG. 32
is a cross section taken along the line C—C in FIG.
31
.
A manufacturing method for the semiconductor device shown in
FIGS. 30
to
32
will now be described. As shown in
FIG. 33
a buried oxide film
102
is first formed on the upper surface of a silicon substrate
101
, and an SOI layer
103
is next formed on the buried oxide film
102
. As shown in
FIG. 34
, an oxide film
104
a
is next stacked on the SOI layer
103
, and a silicon nitride film
106
is next stacked on the oxide film
104
a
. Thereafter, the silicon nitride film
106
is etched by using a resist pattern
114
as an etching mask.
As shown in
FIG. 35
, a resist pattern
115
is next formed on only a P-channel transistor forming region, and boron ions are then implanted into the SOI layer
103
to thereby selectively form a P-type high concentration impurity region
107
in an N-channel transistor forming region.
As shown in
FIG. 36
, the resist patterns
114
and
115
are next removed. Thereafter, a silicon nitride film is formed on the whole surface of the substrate, and is then etched back to leave a sidewall
116
of this silicon nitride film on a surface of the silicon nitride film
106
. Then, anisotropic etching of the SOI layer
103
is performed by using the silicon nitride film
106
and the sidewall
116
as a mask and using the buried oxide film
102
as an etching stopper.
As shown in
FIG. 37
, thermal oxidation is next performed to form an oxide film
109
on the exposed side surface of the SOI layer
103
. Thereafter, the silicon nitride film
106
and the sidewall
116
are etched away. A silicon oxide film having a given thickness is next formed on the whole surface of the substrate, and anisotropic etching is performed by using the SOI layer
103
as an etching mask to form a sidewall
108
.
Thereafter, gate insulating films
104
b
, gate electrodes
110
, sidewalls
111
, an interlayer insulating film
112
, contacts
113
a
, and wirings
113
b
of aluminum or the like are formed to thereby obtain the semiconductor device as shown in
FIGS. 30
to
32
.
In the semiconductor device formed by this method, the upper surface of the SOI layer
103
is damaged by the anisotropic etching which forms the sidewall
108
. Accordingly, in the conventional transistor having a structure in which a sidewall is formed on the side surface of an SOI layer, it is difficult to ensure the reliability of the gate insulating film
104
b
formed by thermally oxidizing the upper surface of the SOI layer
103
having an etching damage.
Further, the sidewall
108
is deposited on only the side surface of the SOI layer
103
. Accordingly, the thickness of a portion of the sidewall
108
formed in the vicinity of an upper edge portion of the SOI layer
103
as shown by symbols A in
FIG. 32
is much smaller than the thickness of the remaining portion of the sidewall
108
. As a result, the distance between the SOI layer
103
and the gate electrode
110
at the upper edge portion of the SOI layer
103
is small, causing a possibility of electric filed concentration and current leakage between the source and drain electrodes.
SUMMARY OF THE INVENTION
The present invention overcomes the above-mentioned drawbacks of the conventional art and it is the purpose of this invention to provide a semiconductor device of a SOI mesa-isolation structure having stable characteristics with suppressed source/drain leak current.
One aspect of the present invention is a semiconductor device including a mesa-isolation silicon layer, formed on an insulating film in which a channel region and source/drain regions are formed. A gate insulating film is formed on the mesa-isolation silicon layer. A conducting layer is formed on the gate insulating film. A sidewall of an insulating material is formed on side surfaces of the mesa-isolation silicon layer, the gate insulating film, and the conducting layer at an end portion of the channel region of the mesa-isolation silicon layer. And a gate electrode is formed on the conducting layer.
Another aspect of the present invention is a semiconductor device as stated above, in which the conducting layer is smaller in area than the gate insulating film.
A further aspect of the present invention is a manufacturing method for a semiconductor device in which an SOI layer, a gate insulating film and a conducting layer, each having a certain thickness, are sequentially stacked on an insulating film. An anisotropic etching is performed by using a predetermined mask pattern to form stacked layers with the same area from the SOI layer, the gate insulating film, and the conducting layer. Side surfaces of at least the SOI layer and the conducting layer are oxidized. The mask pattern is removed. An insulating material is deposited on the insulating film and then anisotropic etching is performed to form a sidewall on the oxidized side surfaces of the SOI layer and the conducting layer. A gate electrode is then formed in contact with the conducting layer.
Another aspect of the present invention is a manufacturing method for a semiconductor device in which an SOI layer, a gate insulating film, a conducting layer, and a nitride film, each having a certain thickness, are sequentially stacked on an insulating film. An anisotropic etching is performed by using a predetermi

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