Method, architecture and circuitry for controlling pulse...

Details Method, architecture and circuitry for controlling pulse... Method, architecture and circuitry for controlling pulse...

2005-07-12

2005-07-12

Burd, Kevin (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

06917661

ABSTRACT:
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a parallel output data signal in response to (i) a first clock signal and (ii) one or more serial data signals. The second circuit may be configured to present the one or more serial data signals and the first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.

REFERENCES:
patent: 4727541 (1988-02-01), Mori et al.
patent: 4809345 (1989-02-01), Tabata et al.
patent: 6167077 (2000-12-01), Ducaroir
patent: 6201829 (2001-03-01), Schneider
patent: 6377575 (2002-04-01), Mullaney et al.

Affiliated with

Also associated with

Rating

Method, architecture and circuitry for controlling pulse... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method, architecture and circuitry for controlling pulse..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, architecture and circuitry for controlling pulse... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3433308