Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-05-28
2001-05-22
Mai, Son (Department: 2818)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
06236230
ABSTRACT:
SUMMARY
The present invention concerns a product term allocation scheme that allows flexibility in the routing of logic signals and/or placement of logic equations in the macrocells of a logic block, similar to that of a programmable logic array (PLA), with a reduced amount of circuitry.
DISCUSSION OF THE BACKGROUND
Current complex programmable logic device (CPLD) product term allocation schemes tend to restrict allocation of product terms to macrocells within a logic block Likewise, placement of logic equations in the macrocells of a logic block is also restricted. To allow for unrestricted allocation-of product terms and placement of logic equations in macrocells, a PLA (Programmable Logic Array) structure may be used. However, in a CPLD, a PLA structure is very costly in both die area and performance.
The main disadvantage of current product term allocation methods is once logic equations are partitioned into a logic block, the macrocells that the logic equations can be placed into are restricted. Logic and/or signal placement software must take into account the distribution of product terms among the logic equations and the sharing of product terms across multiple logic equations. These restrictions can be a problem when attempting to retain fixed pinouts (e.g., input and output signal definitions) after changes are made to an existing design. Since input/output (I/O) cells are connected directly to macrocells in the logic block, logic changes can create a logic block partition that is a legal partition, but will not support the fixed pinout due to the placement restrictions imposed by product term allocation.
The traditional OR array structure typically found in programmable logic arrays allow any product term in the product term array to be steered to and shared by any of the macrocells in a logic block. For most CPLD designs, however, a product term allocation scheme that can allocate on the granularity of a single product term is not needed. The present invention takes advantage of this fact and creates a PLA-type OR structure that steers and shares groups of product terms instead of single product terms.
REFERENCES:
patent: 4878200 (1989-10-01), Asghar et al.
patent: 5450608 (1995-09-01), Steele
patent: 5789939 (1998-08-01), Agrawal et al.
patent: 5969539 (1999-10-01), Veytsman et al.
Cypress Semiconductor Corp.
Mai Son
Maiorana P.C. Christopher P.
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