Method, apparatus, and system for high speed data transfer...

Details Method, apparatus, and system for high speed data transfer... Method, apparatus, and system for high speed data transfer...

2005-01-04

2005-01-04

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C365S233100

Reexamination Certificate

active

06839290

ABSTRACT:
According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

REFERENCES:
patent: 4780891 (1988-10-01), Guerin et al.
patent: 5109304 (1992-04-01), Pederson
patent: 6128248 (2000-10-01), Idei et al.
patent: 6275086 (2001-08-01), Douchi et al.
patent: 6374360 (2002-04-01), Keeth et al.
patent: 6397312 (2002-05-01), Nakano et al.
patent: 20020091958 (2002-07-01), Schoenfeld et al.

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