Method, apparatus, and system for hardware design and synthesis

Details Method, apparatus, and system for hardware design and synthesis Method, apparatus, and system for hardware design and synthesis

2005-08-30

2005-08-30

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S016000

Reexamination Certificate

active

06938237

ABSTRACT:
According to one embodiment of the present invention, a method and system for VLSI hardware design and synthesis is provided in which components provided by a heterogeneous modeling framework are interconnected, based on design specifications of a VLSI, to create a corresponding behavioral VLSI model. The heterogeneous modeling framework contains a first component library including logic functions that can be used to build hardware structural models and a second component library including numeric standard. The created model is simulated, tested, and functionally verified using discrete event domain simulation capabilities provided by the heterogeneous framework. A corresponding structural model is extracted from the tested behavioral VLSI model using a software tool provided by the heterogeneous modeling framework.

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