Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-22
2005-11-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06968521
ABSTRACT:
After automatic cell placement, the following steps are performed before performing automatic inter-cell routing. (S22) Estimated wires having Manhattan-length path are connected between same-node terminals of cells, and detected and counted is a crosstalk error that parallel-wire length is more than a predetermined value. (S23) The detected error is resolved by moving cells closely spaced less than a predetermined interval apart and connected to the error-detected estimated wires; the cell movement data is stored in a storage device; and such processes are repeated N times; and the cell placement data is modified on the basis of the cell movement data corresponding to the minimum value of error-count values of all the N times. (S24) If the minimum value is not 0, (S25) a buffer cell is inserted in the error-detected estimated wire. (S27) Obtained is the wire density of estimated wiring having Manhattan-length path, and if the density is more than a predetermined value, the design-target frame is enlarged in size, and the process returns to the automatic cell placement process.
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Banno Kouji
Ichinose Shigenori
Ushiyama Kenichi
Kik Phallaka
Smith Matthew
Staas & Halsey , LLP
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