Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1999-02-17
2002-09-03
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S236000, C712S226000, C712S227000, C712S230000, C712S242000, C712S243000, C709S241000
Reexamination Certificate
active
06446196
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the data processing field, and more particularly, relates to a method, apparatus and computer program product including one-of and one-of-and-jump instructions used with an embedded processor for processing data communications in a communications system.
DESCRIPTION OF THE RELATED ART
Asynchronous Transfer Mode or ATM is a communication technology whose use is becoming more widespread in some areas while receiving competition from Gigabit Ethernet and Packet Over SONET (POS) in other areas. When the above environments are combined in a single adapter, problems result. In a communications adapter that supports a Packet over SONET physical bus called POS-PHY both cell based protocols and packet based protocols are supported. In addition to both types of protocols, multiple physicals are attached to the bus. Also multiple cell sizes are supported. In this environment, it is necessary to make various different calculations to complete receive and transmit functions for a variety of operational modes.
A need exists for an effective mechanism for making various different calculations for use with processing data communications in a communications system.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a method, apparatus and computer program product for processing data communications in a communications system.
In brief, a method, apparatus and computer program product are provided including one-of and one-of-and-jump instructions for use with processing data communications in a communications system. A one-of instruction control is evaluated. Responsive to the one-of instruction control, a next instruction pointer is generated. A one-of-and-jump instruction is evaluated. Responsive to the one-of-and-jump instruction control, a first next instruction pointer and a second next instruction pointer are generated. The second next instruction pointer is a destination instruction pointer for the one-of-and-jump instruction.
REFERENCES:
patent: 5546522 (1996-08-01), Nishida et al.
patent: 5764941 (1998-06-01), Goto et al.
Pan Daniel H.
Pennington Joan
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