Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-02-11
2008-10-14
Maskulinski, Michael C (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S039000
Reexamination Certificate
active
07437617
ABSTRACT:
A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
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Al-Omari et al., Method, Apparatus, and Computer Program Product in a Processor for Performing In-Memory Tracing Using Existing Communication Paths, filed Feb. 11, 2005.
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Al-Omari Ra'ed Mohammad
Mericas Alexander Erik
Starke William John
Gerhardt Diana R.
International Business Machines - Corporation
Maskulinski Michael C
Miles Neil D
Yee Duke W.
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