Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-01-08
2008-01-08
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000
Reexamination Certificate
active
11055820
ABSTRACT:
A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
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patent: 6324623 (2001-11-01), Carey
patent: 6427195 (2002-07-01), McGowen et al.
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Hrusecky David Allen
Levenstein Sheldon B.
Ronchetti Bruce Joseph
Saporito Anthony
Gerhardt Diana R.
Nguyen T
Yociss Lisa L. B.
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