Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-01
2008-07-01
Sough, Hyung S. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S118000, C711S146000
Reexamination Certificate
active
11184315
ABSTRACT:
A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast local requests to reduce the latency to access data from remote nodes in an SMP computer system. A shared invalid cache coherency protocol state is declined that predicts whether a memory read request to read data in a shared cache line can be satisfied within a local node. When a cache line is in the shared invalid state, a valid copy of the data is predicted to be located in the local node. When a cache line is in the invalid state and not in the shared invalid state, a valid copy of the data is predicted to be located in one of the remote nodes. Memory read requests to read data in a cache line that is not currently in tile shared invalid state are broadcast first to remote nodes. Memory read requests to read data in a cache line that is currently in the shared invalid state are broadcast first to a local node, and in response to being unable to satisfy the memory read requests within the local node, the memory read requests are broadcast to the remote nodes.
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Cantin et al., Method, Apparatus, and Computer Program Product for a Cache Coherency Protocol State that Predicts Locations of Modified Memory Blocks, unkown.
Cantin Jason Frederick
Kunkel Steven R.
Cygiel Gary W
Roberts-Gerhardt Diana L.
Sough Hyung S.
Yee Duke W.
Yociss Lisa L. B.
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