Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-03
2009-10-13
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S013000, C703S014000
Reexamination Certificate
active
07603639
ABSTRACT:
Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive to their time domain variations at respective frequencies. A simulated, substantially noise-only, clock tree output signal is generated in a frequency domain, wherein some components are removed responsive to at least one clock signal frequency and scaled magnitudes of the components. A second simulated clock circuitry output signal is generated responsive to a transfer function of certain clock circuitry. A circuit structure or fabricating process is selected responsive to jitter of the second simulated clock circuitry output signal. The IC may be fabricated using the selected process and may include the selected structure.
REFERENCES:
patent: 6671863 (2003-12-01), Gauthier et al.
patent: 6789237 (2004-09-01), Ismail
patent: 6819192 (2004-11-01), Gauthier et al.
patent: 7005907 (2006-02-01), Ibuka
patent: 2006/0036980 (2006-02-01), Kobayashi
Heydari et al., Analysis of Jitter due to Power Supply Noise in Phase-Locked Loop, 2000, IEEE, pp. 443-446.
Larsson, Patrik, Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise, IEEE Journal of Solid-State Circuits, vol. 36, No. 7, Jul. 2001, pp. 1113-1119.
Voorakaranam, R., Chatterjee, A., Low-Cost Jitter Measurement Technique for Phase-Locked Loops, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, Meeting Date: Aug. 8, 2000-Aug. 11, 2000, vol. 2, pp. 960-965.
Pakbaz Faraydon
Wyatt Stephen Dale
Do Thuan
Doan Nghia M
England Anthony V. S.
Harding Riyon
International Business Machines - Corporation
LandOfFree
Method, apparatus and computer program product for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, apparatus and computer program product for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, apparatus and computer program product for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4095026