Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2006-02-21
2006-02-21
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C711S203000, C711S204000, C711S205000, C711S206000, C711S208000, C711S209000, C711S220000, C711S221000
Reexamination Certificate
active
07003647
ABSTRACT:
A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries (PTEs) is provided for mapping multiple sized pages from a virtual address space to a physical address space. Each of the multiple sized pages is a multiple of a base page size. A region of memory having a starting address and a length is divided into a minimum number of natural blocks for the memory region. Once the region of memory is divided into the natural blocks, page table entries (PTEs) are assigned to map each natural block. Multiple identical PTEs are required to map each natural block greater than a base page size. Only one TLB entry is used to map each natural block.
REFERENCES:
patent: 6112285 (2000-08-01), Ganapathy et al.
Lee et al. “A dynamic TLB management structure to support different page sizes” Aug. 2000, Proceedings of the Second IEEE Asia Pacific Conference, pp 299-302.
Romer et al. “Reducing TLB and Memory Overhead Using Online Superpage Promotion” May 1995, ACM SIGARCH Compute Architecture News, pp 176-187.
Jacobs Brent William
Pieterick James Albert
Pennington Joan
Sparks Donald
Truong Bao Quoc
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