Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-02-28
2006-02-28
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07007258
ABSTRACT:
A technique for generating via array is presented. An origin is set in one corner of a bounding box, and the bounding box is filled, according to at least one spacing rule, starting from the origin, with one or more vias. The bounding box can be defined using a width and a length wherein the bounding box is at least co-extensive with an area for via filling. The bounding box can be larger than the area to be filled, for example, to allow for a metal enclosure or to allow for a non-rectangular area such as a polygon to be filled. When the area to be filled is a polygon, a bounding box of the polygon is filled with vias, any vias outside the polygon can be removed, and any vias crossing a polygon edge can be resized or removed.
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Do Thuan
Sun Microsystems Inc.
Zagorin O'Brien Graham LLP
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