Method and topology for improving signal quality on high...

Details Method and topology for improving signal quality on high... Method and topology for improving signal quality on high...

2006-09-12

2006-09-12

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S026000, C326S027000

Reexamination Certificate

active

07106094

ABSTRACT:
Aspects for improving signal quality on high speed, multi-drop busses are described. The aspects include coupling a source device directly to multiple load devices, wherein there are no resistance components coupled in series between the source device and the multiple load devices. The aspects further include providing a spacing arrangement for the multiple load devices, wherein negative reflections are delayed to minimize deleterious efforts from the negative reflections. Through the present invention, the modified version of a commonly used bus topology achieves extended voltage timing margins in a high speed, multi-drop bus in a straightforward and efficient manner.

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