Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-29
2001-08-07
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06272665
ABSTRACT:
TECHNICAL FIELD
The present invention relates to digital computing, and more particularly to a tool that automatically formats an Engineering Change Order (ECO), in a language suitable for processing by an Electronic Design Automation (EDA) tool, in order to specify metal-only or required design changes to complex hardware data-paths through changes in the netlist.
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as the material appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
Many microchip designs are crafted in similar processes. At the beginning stage of a typical design process, or “front end”, a logic designer uses a Very High Speed Integrated Circuits (VHSIC) Design Language (VHDL) to generate a behavioral description of the chip or chip element. This behavioral description is abstracted to a fairly high level, such as the bus level, and lower-level constructs, such as pins and individual nets, are not present in the front end behavioral description.
The VHDL behavioral model then proceeds through a behavioral synthesizer to create a Register Transfer Language (“RTL”) VIM (VLSI Integrated Model) netlist. This netlist is less abstract that the VHDL behavioral description, and represents, rather than buses, the individual wires connecting logic boxes. The VHDL behavioral description also goes through a logical synthesis, which creates a physical design (“PD”) VIM netlist that is forwarded to the physical designer. The physical designer is involved in the “back end” of the design process, where low-level design decisions are made.
The physical designer typically runs the PD VIM netlist through physical design tools, which places and routes the ultimate, low-level physical components of the chip, such as pins 1 and wires. The design is ultimately sent to a foundry, where the masks for chip processing are finalized. Any changes to the physical chip layout are described in an Engineering Change Order (ECO).
Unfortunately, design flaws often come to light late in the logic verification, physical design, or manufacturing process. Traditionally, there has been no efficient manner of making changes to the chip design once the layout of the thousands of wires has been created at the back end of the chip design process. As stated above, an ECO must be generated in order to make a change to the PD VIM. What is desired is a manner of automatically formatting ECO language, suitable for processing by an Electronic Design Automation (EDA) tool in order to specify metal-only design changes to complex hardware data-paths through changes in the netlist. Such automatic formatting of an ECO would ensure that the source VHDL language does not need resynthesizing in order to change the design. Dispensing with the need to resynthesize VHDL in order to implement design changes allows the designers to avoid the expensive and time consuming prospect of repeating the entire engineering design cycle. As an alternative to resynthesis, the prior art requires the logic designer to identify which of the thousands of wires and pins must be re-routed and re-placed. This process is not only tedious, and time-consuming, but is also error-prone. The present invention eliminates the need to perform either of these prior art methods for implementing relatively late design changes.
SUMMARY OF THE INVENTION
The present invention is a tool and method that automatically formats an Engineering Change Order (ECO) in a language that is suitable for processing by an Electronic Design Automation (EDA) tool, in order to specify metal-only or required design changes to complex hardware data-paths through changes in the netlist. The invention comprises an initial import component that imports a working netlist which serves as the baseline on which the tool operates. The tool further comprises four components: a bus extraction component, an index creation component, a text editor, and an ECO generation component. The bus extraction component extracts one or more buses from the working netlist. The buses to be extracted are specified by the user, usually a logic designer. The tool tabulates these extracted buses into an index table through the operation of its index creation component. The third component, the text editor, is used by the user to modify the index table to create a modified index table that embodies the desired design change. Finally, the ECO generation component automatically reconfigures the modified index table into an ECO, in a format that automated physical design tools may easily read and process.
REFERENCES:
patent: 5956256 (1999-09-01), Rezek et al.
J.D. Atkins, Design Automation for Vertical Adjacency and Horizontal Direct Optimization, IBM Technical Disclosure Bulletin, Mar. 1974, vol. 16, No. 10, U.S.A.
L.G. Bulson, S.R.Hinkelman, and J.M. Korchmar, Application to Consolidate Common Electronic Card Test Fixturing Tasks, IBM Technical Disclosure Bulletin, Oct. 1993, vol. 36, No. 10, U.S.A.
A. Benayoun, A. Bussani, JF. Le Pennec, P. Michel, and C. Pin, Synthesis Optimization by Automatic Very High Design Language Style Change, IBM Technical Disclosure Bulletin, May 1997, vol. 40, No. 05, U.S.A.
Bui Thuy-Linh T.
Johnson Lee E.
International Business Machines - Corporation
Leeuwen Leslie A. Van
Phan Trong
Strasburger & Price LLP
LandOfFree
Method and tool for automatically generating engineering... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and tool for automatically generating engineering..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and tool for automatically generating engineering... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2510531