Method and timing harness for system level static timing...

Details Method and timing harness for system level static timing... Method and timing harness for system level static timing...

2004-12-06

2008-05-13

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07373626

ABSTRACT:
A method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a system design including a design under timing analysis, an external device, and an interface between the design under timing analysis and the external device; (b) generating a timing model for the external device; and (c) constructing a timing test harness for a static timing analysis tool from the timing model for the external device and the design under timing analysis.

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Hui Fu; Static Timing Verification for Complex SoC Design—Part I DDR SDRAM Timing Check in Primetime Revisit; SNUG Singapore 2002; pp. 1-54; Infineon Technologies Asia Pacific, Singapore Design Center Microcontroller Dept., 168 Kallang Way, Singapore 349253.

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