Method and test structure for characterizing sidewall damage...

Details Method and test structure for characterizing sidewall damage... Method and test structure for characterizing sidewall damage...

2000-02-10

2003-07-29

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S679000

Reexamination Certificate

active

06600333

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor manufacturing, and, more particularly, to a method and test structure for characterizing sidewall damage in a semiconductor device.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnect structures. Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnect structures must be made in multiple layers to conserve plot space on the semiconductive substrate.
The conductive interconnect structures are typically accomplished through the formation of a plurality of conductive lines and conductive plugs formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines that connect the various interconnect structures are commonly formed in trenches defined in the dielectric layers.
The term “contact” is generally used to define an interconnect structure (e.g., using polysilicon or metal) to an underlying polysilicon layer (e.g., source/drain or gate region of a transistor), while a “via” denotes a metal to metal interconnect structure. In either case, a contact opening is formed in an insulating layer overlaying the conductive member. A second conductive layer is then formed in the contact opening and electrical communication is established with the conductive member.
One technique for reducing the size of the features formed on the semiconductor device involves the use of copper for the lines and interconnections in conjunction with new dielectric materials having lower dielectric constants than previously achievable with common dielectric material choices. Standard dielectric materials such as silicon dioxide deposited by plasma enhanced chemical vapor deposition (PECVD) using silane or TEOS precursors have dielectric constants greater than 4. The new dielectric materials, commonly referred to as low-k dielectrics, have dielectric constants of 3 or less, and thus, allow greater device densities due to their more efficient isolation capabilities. One such low-k dielectric is sold under the name of Black Diamond, by Applied Materials, Inc.
One problem associated with various low-k dielectrics is the relative difficulty in etching features, such as contact openings or trenches, therein. As a result, the etching process can sometimes damage the sidewalls of the feature defined in the dielectric material. Sidewall damage decreases the effective dielectric constant of the feature and increases leakage current in the device. If the sidewalls are sufficiently damaged, the performance of the device containing the damaged features may be significantly degraded or even entirely compromised, resulting in the scrapping of the device.
During the fabrication of semiconductor devices on a wafer, test structures are commonly formed on the wafer coincident with the discrete semiconductor dice. The test structure includes trenches filled with copper similar in construct to the actual trenches and lines that comprise the functional semiconductor devices. Because the processes used to form functional devices is also used to form the test structures, characteristics of the semiconductor devices may be inferred by evaluating the results of testing on the test structures. Defects that exist in the test structure are likely to be similar in type and distribution to those present in the semiconductor devices. For example, capacitance and leakage tests performed on the test structures give insight as to the capacitance and leakage properties of the semiconductor devices. Test structures may be formed on the same wafer with actual devices, or alternatively, they may be formed on dedicated test wafers on which no saleable devices are present.
One useful parameter that is derivable from such measurements, is the dielectric constant (“k”) of the insulator in which the trenches are formed. Using the known geometry of the test structure, the known dielectric constant of the other dielectric layers, the measured dimensions of each part of the structure (e.g., cross-sectional scanning electron microscope measurements of film thickness, line width, line height, etc.), and the capacitance measurements, the dielectric constant of the low-k material may be determined, typically using commercially available software applications.
Referring to
FIG. 1
, a top view of a prior art test structure
10
is provided. The test structure
10
is referred to in the art as a comb serpentine test structure due to its geometry. Only a portion of the test structure
10
is shown. The test structure
10
includes two combs
20
, each having a base portion
30
, fingers
40
, and a contact pad
45
. The fingers
40
of the combs
20
are interleaved. A serpentine line
50
, having a contact pad
60
weaves through the space between the interleaved combs
20
. Another contact pad (not shown) is present on the end of the serpentine line
50
that is not visible. The contact pads
45
,
60
are suitable areas to which an electrical probe may be attached for testing the electrical characteristics of the test structure
10
. Other prior art test structures only employ the combs
20
and omit the serpentine line
50
.
Using the test structure
10
, the capacitance, and therefrom, the dielectric constant may be determined. Capacitance is measurable using the combs
20
and resistance is measurable using the serpentine line
50
. Deviations between the measured dielectric constant the dielectric constant measured of the insulative layer are generally caused by damage to the insulative layer inflicted during its fabrication. The cause of the damage may vary. For example, an etch tool employed to form the trenches might cause damage localized on the sidewalls of the trenches. Alternatively, a photoresist strip tool, commonly referred to as an asher, might evenly damage the surface of the entire insulative layer.
Relatively severe damage localized on the sidewalls may have the same effect on the bulk dielectric constant than a relatively small amount of damage evenly inflicted across the insulative layer. Because the testing described above measures only the bulk dielectric constant, it is unable to distinguish between these two types of damage. Hence, the root cause of the problem is not easily diagnosed.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a test circuit including a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and second pluralities of fingers are interleaved to define a finger spacing between the first and second pluralities of fingers. The finger spacing in a first one of the test structures being different than the finger spacing in a second one of the test structures.
Another aspect of the present invention is seen in a method for characterizing damage in a semiconductor device. The method includes providing a wafer having an insulative layer and a plurality of test structures formed in the insulative layer. The test structures have different geometries. An electrical characteristic of first and second test structures of the plurality of test structures is determined. Th

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