Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2011-04-12
2011-04-12
Tseng, Cheng-Yuan (Department: 2184)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C713S375000
Reexamination Certificate
active
07925803
ABSTRACT:
Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal.
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Guarnaccia Giuseppe
Mangano Daniele
Pistritto Carmelo
Boller Timothy L.
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tseng Cheng-Yuan
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