Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-09-11
2007-09-11
Lamarre, Guy J. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S025000, C714S048000, C714S057000, C714S042000, C714S799000, C714S712000
Reexamination Certificate
active
10804484
ABSTRACT:
A method, system and article of manufacture to provide debugging of a computer system from firmware. A debugger in a first computer system is initialized during the pre-boot phase of the first computer system, the debugger to operate from a firmware environment of the first computer system. A communication channel of the first computer system is initialized to enable a second computer system to be communicatively coupled to the first computer system. The debugger is entered in response to a debug event. The first computer system is examined with the debugger. In one embodiment, the firmware of the first computer system operates in accordance with an Extensible Firmware Interface (EFI) specification.
REFERENCES:
patent: 5715387 (1998-02-01), Barnstijn et al.
patent: 5850562 (1998-12-01), Crump et al.
patent: 6219782 (2001-04-01), Khan et al.
patent: 6219828 (2001-04-01), Lee
Rothman Michael A.
Zimmer Vincent J.
Abraham Esaw
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Lamarre Guy J.
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