Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2005-02-08
2005-02-08
Donaghue, Larry D (Department: 2154)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C718S103000, C712S219000, C712S228000
Reexamination Certificate
active
06854118
ABSTRACT:
A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A flow marker within instruction information for the first thread received at the instruction information source is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the detection of the flow marker, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
REFERENCES:
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 5325526 (1994-06-01), Cameron et al.
patent: 5357617 (1994-10-01), Davis et al.
patent: 5361337 (1994-11-01), Okin
patent: 5386561 (1995-01-01), Huynh et al.
patent: 5392437 (1995-02-01), Matter et al.
patent: 5404469 (1995-04-01), Chung et al.
patent: 5430850 (1995-07-01), Papadopoulos et al.
patent: 5499349 (1996-03-01), Nikhil et al.
patent: 5524263 (1996-06-01), Griffth et al.
patent: 5528513 (1996-06-01), Vaitzblit et al.
patent: 5553291 (1996-09-01), Tanaka et al.
patent: 5586332 (1996-12-01), Jain et al.
patent: 5630130 (1997-05-01), Perotto et al.
patent: 5742782 (1998-04-01), Ito et al.
patent: 5761522 (1998-06-01), Hisanaga et al.
patent: 5787297 (1998-07-01), Lin
patent: 5809271 (1998-09-01), Colwell et al.
patent: 5809522 (1998-09-01), Novak et al.
patent: 5892959 (1999-04-01), Fung
patent: 5968160 (1999-10-01), Saito et al.
patent: 5983339 (1999-11-01), Klim
patent: 5996085 (1999-11-01), Cheong et al.
patent: 6009454 (1999-12-01), Dummermuth
patent: 6052708 (2000-04-01), Flynn et al.
patent: 6085215 (2000-07-01), Ramakrishnan et al.
patent: 6085218 (2000-07-01), Carmon
patent: 6088788 (2000-07-01), Borkenhagen et al.
patent: 6092175 (2000-07-01), Levy et al.
patent: 6105127 (2000-08-01), Kimura et al.
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6256775 (2001-07-01), Flynn
patent: 6289461 (2001-09-01), Dixon
patent: 6314530 (2001-11-01), Mann
patent: 6330584 (2001-12-01), Joffe et al.
patent: 6470376 (2002-10-01), Tanaka et al.
patent: 6535905 (2003-03-01), Kalafatis et al.
patent: 6625635 (2003-09-01), Elnozahy
patent: 0 346 003 (1989-12-01), None
patent: 0 352 935 (1990-01-01), None
patent: 0 725 335 (1996-08-01), None
patent: 0 747 816 (1996-12-01), None
patent: 0 768 508 (1997-04-01), None
patent: 0 768 608 (1997-04-01), None
patent: 0 827 071 (1998-03-01), None
patent: 0 856 797 (1998-08-01), None
patent: 0 863 462 (1998-09-01), None
patent: 0 864 960 (1998-09-01), None
patent: 0 962 856 (1999-12-01), None
patent: 2311880 (1997-10-01), None
patent: WO9921082 (1999-04-01), None
patent: WO 9921088 (1999-04-01), None
Dean M. Tullsen, et al., “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor” Dept. of Computer Science & Engineering, University of WA, Seattle, WA, May 1994.
Roa P. Pokala, et al., “Physical Synthesis for Performance Optimization”, Vertex Semiconductor, San Jose, CA, Feb. 1992.
Gregory T. Byrd, et al., “Multithreaded Processor Architectures”, Western Carolina University, 8045 IEEE Spectrum, 32 (1995) Aug., No. 8, New York, U.S.
Mark R. Thistle, et al., “A Processor Architecture For Horizon”, Institute for Defense Analyses, Supercomputing Research Center, Lanham, Maryland 20706, Sep. 1988.
Steere D, et al., “A Feedback-driven Proportion Allocator for Real-Rate Scheduling”,Third Symposium on Operating Systems Design and Implementations, Feb. 22-25, 1999, pp. 145-158, XP002153159.
Intel, “P6 Family of Processors”,Hardware Developer's Manual, Sep. 1998, XP-002153160.
IBM, “Improved Dispatching in a Rendering Context Manager”,IBM Technical Disclosure Bulletin, Dec. 1990, pp. 131-134, vol. 33, No. 7, XP000108363 ISSN: 0018-18689, Armonk, NY.
Farrens, Mk; Pleszkun, Ar., “Strategies for Archieving Improved Processor Throughput”,The 18th Annual International Symposium on Computer Architecture, May 27-30, 1991, pp. 362-369.
Mendelson, A; Berkerman, M., “Design Alternatives of Multithreaded Architecture”,International Journal of Parallel Programming, Dec. 9, 1996, vol. 27, No. 3, pp. 161-193, Pullenum Publishing Corporation.
James Laudon, Anoop Gupta and Mark Horowitz, “Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors”,Multithreaded Computer Architecture; A Summary of the State of the Art, chapter 8, pp. 167-200, Kluwer Academic Publishers 1994.
Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo and Rebecca L. Stammm, “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor”,Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 22-24, 1996, pp 191-202.
Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante and Shiafun Liu, “Evaluation of Multithreaded Uniprocessors for Commercial Application Environments”,Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 22-25, 1996, pp 203-212.
Manu Gulati and Nader Bagherzadeh, “Performance Study of a Multithreaded Superscalar Microprocessor”,Proceedings Second International Symposium on High-Performance Computer Architecture, Feb. 3-7, 1996, pp. 291-301.
R. Guru Prasadh and Chuan-Lin Wu, “A Benchmark Evaluation of a Multi-Threaded RISC Processor Architecture”,1991 International Conference on Parallel Processing, pp 184-191.
Peter Song, “Multithreading Comes of Age”,Microdesign Resources, Jul. 14, 1997, pp. 13-18.
Dennis Lee, Jean-Loup Baer, Brad Calder and Dirk Grunwald, “Instruction Cache Fetch Policies for Speculative Execution”, 22nd International Symposium on Computer Architecture, Jun. 1995.
Ruediger R. Asche, “Multithreading for Rookies”, Http://www.microsoft.com/win32der/base/threads.htm, Jul. 31, 1998.
Simon W. Moore, “Multithreaded Processor Design”, Kluwer Academic Publishers, 1996.
Dongwook K., et al., “A Partitioned On-Chip Virtual Cache For Fast Processors”, Journal of Systems Architecture, Elsevier Science Publishers BV., Amsterdam, NL, vol. 43, No. 8, May 1, 1997 (1997-05-01), pp. 519-531, XP000685730.
International Search Report-PCT/US00-10800-Feb. 20, 2001.
Rosenberg Dictionary of Computers, Information Processing and Telecommunications, pp. 299-300, 1987.
Fisch Robert D.
Kalafatis Stavros
Kyker Alan B.
Blakely , Sokoloff, Taylor & Zafman LLP
Donaghue Larry D
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