Method and system of semiconductor fabrication fault analysis

Details Method and system of semiconductor fabrication fault analysis Method and system of semiconductor fabrication fault analysis

2006-04-18

2006-04-18

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Quality evaluation

Reexamination Certificate

active

07031860

ABSTRACT:
A system and method for semiconductor fabrication fault analysis. The storage device stores test records. The program module receives a study lot identity, acquires suspect fabrication issues corresponding to the study lot identity, acquires a number of comparative wafer lot identities processed by the same fabrication tool and fabrication recipe for each fabrication issue, defines the comparative wafer lot identities having the same failed cluster groups as similar failed lot identities, calculates a similarity score for each similar failed lot identity, calculates a causal score according to the similarity scores for each suspect fabrication issue, and arranges the suspect fabrication issues according to causal scores thereof.

REFERENCES:
patent: 6421574 (2002-07-01), Steffan et al.
patent: 6610550 (2003-08-01), Pasadyn et al.
patent: 2002/0161532 (2002-10-01), Dor et al.

Affiliated with

Also associated with

Rating

Method and system of semiconductor fabrication fault analysis does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system of semiconductor fabrication fault analysis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system of semiconductor fabrication fault analysis will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3603226