Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-10
2003-07-22
Smith, Matthew (Department: 2811)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06598206
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the physical design of semiconductor integrated circuits, and more particularly to a physical design methodology and tools which automatically modify power shapes to improve overall wireability in congested areas and provide access to inaccessible pins or logic service terminals (LSTs).
2. Description of the Related Art
During physical design of integrated circuits, automatic placement tools are typically used to obtain placement for functional library cells in the design. Automatic power routing tools are typically used to route the power rails of the design. Congestion analysis tools are used to analyze the resulting design after placement and power routing has been completed and prior to final signal wiring. Congestion analysis gives an early indication of the likely success of signal wiring. International Business Machines Corporation of Armonk, N.Y., USA provides placement, power routing, congestion analysis and detail wiring in their commercially available ChipBench tool suite. A cell-3 brand automatic layout tool (available from Cadence Design of Santa Clara, Calif., USA) provides similar functionality. In highly congested areas of the design, it is desirable to reduce the congestion to improve the success of automatic wiring. Typical power shapes tend to be periodic rails on each metal level spanning large areas of the design. Power rails on adjacent metal levels are connected by power vias at their intersections forming a three dimensional power grid. Congestion could be reduced by using significantly smaller power shapes during power routing. However, this dramatically increases the number of power shapes, which impacts the storage and performance of the layout related tools. Thus, it is an object of the invention to utilize unmodified power rail shapes whenever possible to maintain current tool performance and memory usage and at the same time reduce congestion by modifying power shapes in highly congested areas.
Additionally, input/output LSTs (pins or logic service terminals) of placed library cells sometimes become blocked by the power rails during power routing, making connection impossible. It is desirable to ensure all pins are accessible prior to automatic signal wiring.
Reducing congestion and improving pin accessibility increases the ability to complete automatic wiring successfully. Thus, there has arisen a need for an efficient method of modifying power shapes to reduce congestion and improve wireability in an application specific integrated circuit (ASIC) design.
SUMMARY OF THE INVENTION
It is therefore one object of this invention to provide an automatic physical design tool to reduce wiring congestion and improve wireability in an ASIC design that is independent of the underlying design methodology.
It is yet another object of the invention to provide an automatic physical design tool that improves pin accessibility and therefore increases wireability in an ASIC design that is independent of the underlying design methodology.
It is yet another object of this invention to provide a physical design methodology that has no major impact on the memory requirements or performance of other tools in the layout tool suite used for a given ASIC design.
In accordance with these and other objectives, the present invention provides a design tool and methodology which detect congested wiring areas of a design or inaccessible pins of a design, and replaces the power rail structure(s) in these areas with a modified power structure(s) that reduces wiring congestion and allows pin access. In a first embodiment of the invention, a three-dimensional model of the ASIC design is used. The inputs to the invention are the various shapes currently in the ASIC design and their interconnections which includes, but is not limited to, power shapes, circuit placement, pins, and abstracted blockages. For all inaccessible pins blocked on the metal level above by a power rail, the invention removes select areas of the power rail on the metal level directly above each pin while maintaining interconnection with other power shapes. The first embodiment operates in an iterative manner from metal level to metal level until complete.
Another embodiment of the invention includes an alternative power pattern for the power rails to relieve wiring congestion in affected areas of an ASIC design. This embodiment of the invention determines areas of the design that benefit by changing the power rail pattern from an initial pattern to an alternative pattern such as stitches or staples. The second embodiment can operate in an iterative manner to achieve a desired wireability result.
ASIC images which include power patterns and image metals are combined to create an ASIC power grid from chip wire bond pads or chip C4 balls (depending on the ASIC package requested) to the ASIC cells. These images are pre-designed and not modified during a typical ASIC physical design process so as not to impact the ASIC chip turn-around-time. The image and power patterns are analyzed for IR drop and electromigration (EM) using worst case power requirements for each image/package offering during the early development of each new ASIC technology. “RailMill” tool, available from Synopsys Inc., Mountain View, Calif., USA is a commercial reliability simulator that analyzes power network voltage drop of an IC network. The image power grid described in this invention was designed and analyzed for IR drop and EM using the M
2
power staple pattern described below. The M
2
power staple pattern, when compared with the other M
2
power patterns of stitches or rails, is the least electrically robust though not significantly due to other pinch points in the power grid on other levels. Therefore the process described in this invention of converting M
2
power rails to either stitches or staples is electrically accounted for in the initial image analysis and not required to be re-analyzed after each change to the M
2
power grid.
Thus, the invention provides a method and system for modifying power rails of an integrated circuit to improve wireability. This is accomplished by initially generating a model of a three-dimensional rail based power grid. Next, analysis of the design is performed as to the location of the power rails in relation to neighboring elements (e.g., pins, rails, blockages, etc.) with respect to congestion and pin accessibility that affects a predefined wireability. Finally, modification of a segment of each power rail that affects wireability is performed so that required power supply potential to the neighboring elements remains unaffected.
REFERENCES:
patent: 6397170 (2002-05-01), Dean et al.
Darden Laura R.
Gould Scott W.
Ryan Patrick M.
Urish Steven J.
Do Thuan
Kotulak, Esq. Richard M.
McGinn & Gibb PLLC
Smith Matthew
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