Method and system of minimizing simultaneous switching noise in

Details Method and system of minimizing simultaneous switching noise in Method and system of minimizing simultaneous switching noise in

1998-12-15

2000-06-06

Santamauro, Jon

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 82, H03K 1716

Patent

active

060723297

ABSTRACT:
A low noise system for transmitting data includes a data bus (12) and a transmitting system (14). The data bus (12) has a plurality of data lines (20) and parity line (22). The transmitting system (14) is coupled to the data bus (12) and operable to receive a data set, store a previously adjusted data set transmitted on the data lines, generate a parity signal based on the data set and the previously adjusted data set and generate an adjusted data set based on the data and the parity signal. The adjusted data set is transmitted on the data lines (20) and the parity signal is transmitted on the parity line (22).

REFERENCES:
patent: 4477904 (1984-10-01), Thorsrud
patent: 4924120 (1990-05-01), Schenck
patent: 4959563 (1990-09-01), Schenck
patent: 5066872 (1991-11-01), Schenck
patent: 5118971 (1992-06-01), Schenck
patent: 5214330 (1993-05-01), Okazaki
patent: 5220208 (1993-06-01), Schenck
patent: 5789944 (1998-08-01), Choy et al.

Affiliated with

Also associated with

Rating

Method and system of minimizing simultaneous switching noise in does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system of minimizing simultaneous switching noise in , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system of minimizing simultaneous switching noise in will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2216446