Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-12-22
2001-06-12
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S637000, C438S672000
Reexamination Certificate
active
06245664
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor devices, and more particularly to a method and system of interconnecting conductive elements in an integrated circuit.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are often constructed of solid state components. Solid state components have no moving parts, but operate based on the movement of charged carriers. As a result, solid state components are extremely reliable, very small and relatively inexpensive.
Solid state components may be transistors, capacitors, resistors and the like based on or utilizing semiconductor materials. Such components are typically formed on a wafer of substrate material as part of an integrated circuit. In the integrated circuit, the solid state components are suitably laid out, isolated and interconnected to form memory arrays and other types of useful circuits. The components are conventionally isolated by insulation layers formed between active areas, leads and other conductive regions and interconnected by conductors passed through the insulation layers to connect the active areas, leads and other conductive regions at specified locations.
To allow vertical interconnection of components in an integrated circuit, an active area, lead or conductive region is typically enlarged at a contact point to horizontally overlap a contact point of the connecting active area, lead or conductive region. This enlargement of contact points, however, increases the size of the integrated circuit and causes difficulty in laying out the integrated circuit. The enlargement is especially problematic for DRAM cells and other types of circuits that have an array of repeatedly duplicated components and wiring. In addition, the enlarged contact points increases parasitic capacitance of active areas, leads and conductive regions, which reduces the speed of the integrated circuit.
Alternatively, an intermediate wiring layer, or pad, has been used to interconnect active areas, leads or conductive regions of an integrated circuit. In this arrangement, the intermediate pad is typically disposed between and horizontally overlaps the contact points of active areas, leads or conductive regions to be interconnected. A first vertical conductor connects a first active area, lead or conductive region to a first side of the intermediate pad and a second vertical conductor connects a second active area, lead or conductive region to a second side of the intermediate pad. The intermediate pad, however, requires additional material and process steps to fabricate, including relatively expensive photo lithography masking steps.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen in the art for an improved interconnect between active areas, leads or conductive regions of an integrated circuit. The present invention provides a method and system of interconnecting conductive elements in an integrated circuit that substantially eliminate or reduce problems associated with previous systems and methods.
In accordance with the present invention, conductive elements of an integrated circuit may be interconnected by forming a lower conductive element having a lower contact section with a width not more than substantially that of an adjacent section of the lower conductive element. A first insulation layer may be formed outwardly of the lower conductive element. An upper conductive element may be formed outwardly of the insulation layer. The upper conductive element may have a upper contact section with a width not more than substantially that of an adjacent section of the upper conductive element. A second insulation layer may be formed outwardly of the first insulation layer and the upper conductive element. A contact hole may be formed in the first and second insulation layers exposing a lower contact area of the lower contact section and an upper contact area of the upper contact section. An interconnect may be formed in the contact hole connecting the contact areas of the lower and upper conductive elements. The interconnect may have a substantially uniform width between the lower and upper conductive elements.
More specifically, in accordance with one embodiment of the present invention, the lower contact section may be substantially uniform in width to the adjacent section of the lower conductive element. The upper contact section may be substantially uniform in width to the adjacent section of the upper conductive element. In this and other embodiments, the contact sections may be non overlapping. The lower contact area may substantially comprise a top of the lower conductive element and the upper contact area may substantially comprise a sidewall of the upper conductive element.
In accordance with the one aspect of the present invention, three or more conductive elements may be connected by the interconnect. Each of the conductive elements may have a contact section with a width not more than substantially that of an adjacent section of the conductive element. The interconnect may have a substantially uniform width between each set of conductive elements.
Important technical advantages of the present invention include providing an improved integrated circuit. In particular, the integrated circuit may comprise conductive elements having contact sections with a width not more than substantially that of an adjacent section of the conductive elements. Thus, the conductive elements may be interconnected without enlarged contact sections that increase size and reduce performance of the integrated circuit. In addition, the integrated circuit may be more easily laid out.
Another technical advantage of the present invention includes providing an improved method and system of interconnecting conductive elements in an integrated circuit. In particular, an interconnect may overlap a first conductive element and abut a second conductive element. Thus, the conductive elements need not overlap or be connected by an intermediate wiring layer. Accordingly, manufacturing costs of the integrated circuit is reduced.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 5726098 (1998-03-01), Tsuboi
patent: 5759914 (1998-06-01), Park
patent: 5824579 (1998-10-01), Subramanian et al.
patent: 5859264 (1999-04-01), Teo
patent: 5972788 (1999-10-01), Ryan et al.
patent: 6022804 (2000-02-01), Yano et al.
patent: 6180514 (2001-01-01), Yeh et al.
patent: 4-355951 (1992-12-01), None
Brady III Wade James
Quach T. N.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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