Method and system of implementing an early data dependency resol

Details Method and system of implementing an early data dependency resol Method and system of implementing an early data dependency resol

1996-11-04

1998-09-22

Eng, David Y.

G06F 938

Patent

active

058128123

ABSTRACT:
A method and system of implementing an early data dependency resolution mechanism for a high-performance data processing system that utilizes out-of-order instruction issue is disclosed. In accordance with the present disclosure, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines, and each of these cache lines is capable of storing multiple instructions. The register-dependency cache contains an identical number of cache lines as in the instruction cache, and each of the cache lines within the register-dependency cache is capable of storing an identical number of register-dependency units as instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified utilizing an Instruction Dispatch Unit. Each of the identified register-dependency units is then translated to its respective instruction utilizing a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle.

REFERENCES:
patent: 5463746 (1995-10-01), Brodnax et al.
patent: 5655133 (1997-08-01), Dupree et al.
Gurindar, Sohi, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computer", 1900 IEEE, pp. 349-359.

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