Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
1999-06-29
2002-03-19
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
Reexamination Certificate
active
06360339
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to the field of data communication networks. More particularly, the present invention relates to a system and method of dynamically selecting a data coalescing technique that optimally transports data between a network controller and computer system memory, based on the capabilities of the computer system and its system bus loads.
2. Description of Related Art
Keeping up with the increasing traffic in data communications networks is an ever-present challenge. This challenge is exacerbated by the need to also achieve optimal computer system performance while maintaining network reliability.
FIG. 1
(Prior Art) illustrates the basic components of a networked computer system
100
. The computer system implements a Peripheral Component Interconnect (PCI) bus infrastructure
105
to communicate between the various components. The microprocessor
160
is connected to the PCI bus
105
and is supported by the system main memory (RAM)
170
and read-only memory (ROM)
155
. The main memory
170
includes the operating system of the computer (OS)
190
as well as a network operating system
175
, a transport mechanism
185
, and a protocol support
180
to achieve network communications pursuant to the conventional seven-layered Open Systems Interconnect model. The transfer of data between components is controlled by the memory manager
150
, which is connected to PCI bus
105
and regulates Direct Memory Access (DMA) transfer operations.
As shown in
FIG. 1
, the computer system
100
interfaces with the network link
195
via the network controller
110
. The network controller
110
is coupled to the PCI bus
105
and directly attaches to the network link
195
. Typically, the system
100
engages memory manager
150
to utilize DMA transport mechanisms to transfer data between the system main memory
170
and the network controller
195
via the PCI bus
105
.
FIG. 2
depicts a data packet
210
to be transferred from main memory
170
to the network controller
195
. The packet
210
is configured in accordance with the Network Driver Interface Specification (NDIS), developed jointly by Microsoft and 3Com (see
Network Driver Interface Specification
3.0, released in 1989). NDIS provides a standardized control interface for network controller drivers and protocol drivers and specifies a layered protocol stack for configuring network-bound packets. Accordingly, NDIS packets
210
have pointers
212
,
214
,
216
indicating the location of NDIS buffers
230
,
240
,
250
. These buffers
230
,
240
,
250
are locations in main memory where the data to be transferred is actually stored.
Generally, each NDIS packet
210
comprises data from the 3 separate NDIS buffers
230
,
240
,
250
. For example, in transferring a typical 1514-byte frame emerging from a TCP/IP protocol stack, the NDIS interface initially assembles the frame data as an NDIS packet
210
. Thus, 14 bytes of TCP/IP data reside in the first NDIS buffer
230
, 40 bytes of the data reside in the second NDIS buffer
240
, and 1460 bytes of the data reside in the third NDIS buffer
250
.
To route the NDIS packets
210
from main memory
170
to the network controller
110
, and ultimately to their network destination, the packets
210
must first be transported to the PCI bus
105
. This operation can be accomplished by incorporating data coalescing techniques. Essentially, coalescing techniques copy the content of one or more memory locations to another memory location. One such data coalescing technique is demonstrated in FIG.
2
. This technique, referred to as “smart coalescing”, incorporates a Transmit Control Block (TxCB)
220
data structure and an immediate data memory area
225
, which attaches to the TxCB
220
. The TxCB
220
is a specific data structure used by the system hardware to identify the location of desired data. Using this smart coalescing technique, the system accesses the NDIS buffers
230
,
240
,
250
, and if the contents of these buffers are small enough, the system copies their contents into the immediate data memory area
225
and then transfers the data to the PCI bus
105
. As illustrated in
FIG. 2
, because NDIS buffer
230
contains 14 bytes of data while NDIS buffer
240
contains 40 bytes of data, the contents of these buffers are small enough to be copied
231
,
232
,
241
,
242
into immediate data memory area
225
.
If a buffer's content is too large to be copied, the smart coalescing directs the system to map a pointer
260
to the buffer and to store the pointer
260
information in the TxCB
220
. The system then transfers
270
the pointer
260
information, as well as the data in the buffer
250
, onto the PCI bus
105
as one block of data. For example, because NDIS buffer
250
is so large (e.g., 1460 bytes), as shown in
FIG. 2
, the smart coalescing technique maps a pointer
260
to the buffer
250
and stores it in the TxCB
220
. The system then reads the pointer
260
in TxCB
220
and transfers
270
the pointer
260
information and the contents of buffer
250
onto the PCI bus
105
without copying.
Therefore, for every TCP/IP frame to be transferred, the smart coalescing technique copies the contents of 2 of the 3 buffers (i.e.,
130
and
140
) for a total of 54 bytes. However, copying data onto the PCI bus
105
, even as little as 54 bytes worth, requires microprocessor
160
intervention, which tasks the microprocessor
160
and ultimately degrades system performance. This is supported by recent performance tests, which indicate that the most efficient data coalescing technique performs no coalescing whatsoever. Rather, by physically mapping all of the NDIS buffers
230
,
240
,
250
and transferring them on the PCI bus
105
as a single TCP/IP frame, the microprocessor
160
is not utilized and system performance increases significantly.
FIG. 3
illustrates a non-coalescing technique. This technique instructs the system to read the pointer information
322
,
324
,
326
of the TxCB
120
, which reference the NDIS buffers
230
,
240
,
250
, respectively. The pointer information
322
,
324
,
326
is then transferred
327
to the PCI bus
105
as one block of data. In addition, the system, based on the pointer information
322
,
324
,
326
, maps the data contained in each of the NDIS buffers
230
,
240
,
250
, and automatically transfers
328
,
329
,
330
the data onto the PCI bus
105
as 3 additional data blocks. As such, this non-coalesce technique requires 4 separate transfers to transmit the 4 blocks of data across the PCI bus
105
. Because the data is not coalesced or copied onto the PCI bus
105
, but is physically mapped and transferred onto the bus
105
, the data is transferred without any microprocessor
160
intervention. As such, there is minimal microprocessor
160
utilization.
One potential problem with this non-coalesce technique is its tendency to burden the PCI bus
105
. As shown above, the non-coalesce technique requires 4 transfers across the PCI bus
105
to accommodate 1 TCP/IP frame. Each transfer commits the system to negotiate for the control of the PCI bus
105
in order to transfer each data block. If the PCI bus
105
is under heavy usage or cannot sustain a heavy steady state load of data, data may not reach the network controller within a reasonable amount of time. For example,
FIG. 4
depicts that, before being transmitted across the network, the PCI bus
105
funnels data into the network controller FIFO buffer
410
which contains a transmit threshold
405
. The transmit threshold
405
is the level that the data in the buffer
410
must accumulate to, before the buffer
410
begins transmitting data. Clearly, the lower the transmit threshold
405
, the lower the transmission delays, the higher the throughput, and the more efficient the network. To this end, the network controller
110
begins transmitting across the physical network link
195
as soon as the buffered data reaches the transmit threshold
405
. Such transmi
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