Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-04
2010-10-05
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07810053
ABSTRACT:
The present invention relates to a novel active leakage power reduction technique, referred to as the dynamic power cutoff technique (DPCT). The DPCT method of the present invention can reduce active leakage, standby leakage, and dynamic power by applying the dynamic power cutoff technique to a circuit. In the method and system for dynamic power cutoff for active leakage reduction in circuits of the present invention, a switching window is determined for each gate, during which a gate makes its transitions. For example, the switching window can be determined by static timing analysis. Then, the circuit is optimally partitioned into different groups based on the minimal switching window (MSW) of each gate. Finally, power cutoff transistors are inserted into each group to control the power connections of that group. Each group is turned on only long enough for a wavefront of changing signals to propagate through that group. Since each gate is only turned on during a small timing window within each clock cycle, this significantly reduces active leakage power.
REFERENCES:
patent: 5983007 (1999-11-01), Agrawal
patent: 7454738 (2008-11-01), Banerjee et al.
patent: 7665047 (2010-02-01), Orshansky et al.
patent: 2004/0060022 (2004-03-01), Allen et al.
Yu et al., “A Novel Dynamic Power Cutoff Technique (DPCT) for Active Leakage Reduction in Deep Submicron CMOS Circuits,” IEEE, Oct. 4-6, 2006, pp. 214-219.
Bhunia et al., “A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating”, Proc. of the Design Automation Conf. 479-484 (2005).
Burd et al., “A Dynamic Voltage Scaled Microprocessor System”, IEEE Journal of Solid-State Circuits, 35 (11):1571-1580 (2000).
Cao et al., “New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation”, IEEE Custom Integrated Circuits Conf. 201-204 (2000).
Chen et al., “0.18um Dual Vt. MOFET Process and Energy-Delay Measurement”, Proc. of the 1996 Int'l, Electron Devices Meeting 851-854 (1996).
Halter et al., “A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits”, IEEE 1997 Custom Integrated Circuits Conf. 475-478 (1997).
Johnson et al., “Leakage Control with Efficient use of Transistor Stacks in Single Threshold CMOS”, Proc. Design Automation Conf. 442-445 (1999).
Kawaguchi et al., “A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current”, IEEE J Solid-State Circuits 35(10):1498-1501 (2000).
Raja et al., “CMOS Circuit Design for Minimum Dynamic Power of Highest Speed”, Proc. Int'l. Conf. on VLSI Design 1035-1040 (2004).
Takahashi et al., “A 60-mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme”, IEEE J Solid-State Circuits 33(11):1772-1780 (1998).
Wei et al., “Design and Optimization of Low Voltage High Performance Dual Thershold CMOS Circuits”, Proc. Design Automation Conf., 489-494 (1998).
Bushnell Michael
Yu Baozhen
Porzio, Bromberg & Newman
Siek Vuthe
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