Method and system of controlling a cache memory by...

Details Method and system of controlling a cache memory by... Method and system of controlling a cache memory by...

2004-11-15

2009-06-23

Sough, Hyung S (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S122000, C711S140000

Reexamination Certificate

active

07552287

ABSTRACT:
A cache memory control unit that controls a cache memory comprises: a PF-PORT22and MI-PORT21that receive a prefetch request and demand fetch request issued from a primary cache; and a processing pipeline27that performs swap processing when the MI-PORT21receives a demand fetch request designating the same memory address as that designated by a prefetch request that has already been received by the PF-PORT22, the swap processing being performed so that an MIB28that has been ensured for replying the prefetch request is used for a reply to the demand fetch request following the prefetch request.

REFERENCES:
patent: 6625697 (2003-09-01), Stoess et al.
patent: 6643745 (2003-11-01), Palanca et al.
patent: 2-133842 (1990-05-01), None
European Office Action dated Aug. 11, 2006.
European Communication dated Aug. 1, 2008 in corresponding European Application No. 08152649.3-1229/1942416.

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